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@@ -29,16 +29,14 @@
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#include <common.h>
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#include <asm/sizes.h>
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-#include <asm/arch/at91sam9g45.h>
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+#include <asm/io.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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-#include <asm/arch/at91_pio.h>
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+#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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-#include <asm/arch/io.h>
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-#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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@@ -54,9 +52,9 @@ DECLARE_GLOBAL_DATA_PTR;
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static void pm9g45_nand_hw_init(void)
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{
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unsigned long csa;
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- at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
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- at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable CS3 */
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csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
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@@ -80,7 +78,7 @@ static void pm9g45_nand_hw_init(void)
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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- writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer);
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+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
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#ifdef CONFIG_SYS_NAND_READY_PIN
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/* Configure RDY/BSY */
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@@ -95,7 +93,7 @@ static void pm9g45_nand_hw_init(void)
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#ifdef CONFIG_MACB
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static void pm9g45_macb_hw_init(void)
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{
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- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/*
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* PD2 enables the 50MHz oscillator for Ethernet PHY
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@@ -106,7 +104,7 @@ static void pm9g45_macb_hw_init(void)
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at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
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/* Enable clock */
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- writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer);
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+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
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/*
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* Disable pull-up on:
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@@ -131,22 +129,22 @@ static void pm9g45_macb_hw_init(void)
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int board_init(void)
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{
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- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable Ctrlc */
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console_init_f();
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- writel((1 << AT91SAM9G45_ID_PIOA) |
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- (1 << AT91SAM9G45_ID_PIOB) |
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- (1 << AT91SAM9G45_ID_PIOC) |
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- (1 << AT91SAM9G45_ID_PIODE), &pmc->pcer);
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+ writel((1 << ATMEL_ID_PIOA) |
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+ (1 << ATMEL_ID_PIOB) |
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+ (1 << ATMEL_ID_PIOC) |
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+ (1 << ATMEL_ID_PIODE), &pmc->pcer);
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/* arch number of AT91SAM9M10G45EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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- at91_serial_hw_init();
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+ at91_seriald_hw_init();
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#ifdef CONFIG_CMD_NAND
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pm9g45_nand_hw_init();
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#endif
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@@ -188,7 +186,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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- rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
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+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
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#endif
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return rc;
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}
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