lwmon5: watchdog POST fix

Use the GPT0_MASKx registers as the temporary storage for watch-dog
timer POST test instead of GPT0_COMPx. The latter
(GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header.

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

include/configs/lwmon5.h

@@ -75,8 +75,8 @@
 /*
  * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
- * for logbuffer only.
+ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
+ * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  */
 #define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
@@ -91,9 +91,9 @@
 
 /* Additional registers for watchdog timer post test */
 
-#define CFG_DSPIC_TEST_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP5)
-#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP4)
-#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP5)
+#define CFG_DSPIC_TEST_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
+#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK2)
+#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
 #define CFG_WATCHDOG_MAGIC	0x12480000
 #define CFG_WATCHDOG_MAGIC_MASK	0xFFFF0000
 #define CFG_DSPIC_TEST_MASK	0x00000001
@@ -251,6 +251,7 @@
 
 #define CFG_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
 #define CONFIG_LOGBUFFER
+/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 #define CONFIG_ALT_LH_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP1)
 #define CONFIG_ALT_LB_ADDR	(CFG_OCM_BASE)
 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

include/ppc440.h

@@ -1437,6 +1437,13 @@
 #define GPT0_COMP2			0x00000088
 #define GPT0_COMP1			0x00000084
 
+#define GPT0_MASK6			0x000000D8
+#define GPT0_MASK5			0x000000D4
+#define GPT0_MASK4			0x000000D0
+#define GPT0_MASK3			0x000000CC
+#define GPT0_MASK2			0x000000C8
+#define GPT0_MASK1			0x000000C4
+
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_USB2D0CR                 0x0320
 #define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */