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@@ -65,6 +65,56 @@ char *get_reset_cause(void)
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}
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}
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}
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}
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+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
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+#if defined(CONFIG_MX53)
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+#define MEMCTL_BASE ESDCTL_BASE_ADDR;
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+#else
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+#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
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+#endif
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+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
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+static const unsigned char bank_lookup[] = {3, 2};
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+
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+struct esd_mmdc_regs {
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+ uint32_t ctl;
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+ uint32_t pdc;
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+ uint32_t otc;
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+ uint32_t cfg0;
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+ uint32_t cfg1;
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+ uint32_t cfg2;
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+ uint32_t misc;
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+ uint32_t scr;
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+ uint32_t ref;
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+ uint32_t rsvd1;
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+ uint32_t rsvd2;
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+ uint32_t rwd;
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+ uint32_t or;
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+ uint32_t mrr;
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+ uint32_t cfg3lp;
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+ uint32_t mr4;
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+};
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+
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+#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
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+#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
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+#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
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+#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
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+#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
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+
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+unsigned imx_ddr_size(void)
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+{
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+ struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
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+ unsigned ctl = readl(&mem->ctl);
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+ unsigned misc = readl(&mem->misc);
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+ int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
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+
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+ bits += ESD_MMDC_CTL_GET_ROW(ctl);
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+ bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
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+ bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
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+ bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
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+ bits += ESD_MMDC_CTL_GET_CS1(ctl);
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+ return 1 << bits;
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+}
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+#endif
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+
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#if defined(CONFIG_DISPLAY_CPUINFO)
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#if defined(CONFIG_DISPLAY_CPUINFO)
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const char *get_imx_type(u32 imxtype)
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const char *get_imx_type(u32 imxtype)
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