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@@ -149,7 +149,7 @@ DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
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DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
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# bit3-0 : 0000, required
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# bit7-4 : 0010, M_ODT assertion 2 cycles after read
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-# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read
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+# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
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# bit15-12: 0100, internal ODT assertion 4 cycles after read
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# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
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# bit31-20: 0 , required
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