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@@ -531,6 +531,7 @@ static int mvgbe_send(struct eth_device *dev, void *dataptr,
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struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
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void *p = (void *)dataptr;
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u32 cmd_sts;
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+ u32 txuq0_reg_addr;
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/* Copy buffer if it's misaligned */
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if ((u32) dataptr & 0x07) {
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@@ -552,7 +553,8 @@ static int mvgbe_send(struct eth_device *dev, void *dataptr,
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p_txdesc->byte_cnt = datasize;
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/* Set this tc desc as zeroth TXUQ */
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- MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
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+ txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
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+ writel((u32) p_txdesc, txuq0_reg_addr);
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/* ensure tx desc writes above are performed before we start Tx DMA */
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isb();
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@@ -583,6 +585,7 @@ static int mvgbe_recv(struct eth_device *dev)
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struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
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u32 cmd_sts;
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u32 timeout = 0;
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+ u32 rxdesc_curr_addr;
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/* wait untill rx packet available or timeout */
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do {
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@@ -637,8 +640,8 @@ static int mvgbe_recv(struct eth_device *dev)
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p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
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p_rxdesc_curr->byte_cnt = 0;
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- writel((unsigned)p_rxdesc_curr->nxtdesc_p,
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- (u32) &dmvgbe->p_rxdesc_curr);
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+ rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
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+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
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return 0;
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}
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