Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

board/esd/cpci405/Makefile

@@ -29,6 +29,7 @@ endif
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	+= ../common/cmd_loadpci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/cpci405/cpci405.c

@@ -20,8 +20,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <command.h>
@@ -31,16 +32,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);	/*cmd_boot.c*/
-#if 0
-#define FPGA_DEBUG
-#endif
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+#undef FPGA_DEBUG
 
 /* fpga configuration data - generated by bin2cc */
 const unsigned char fpgadata[] =
 {
-#ifdef CONFIG_CPCI405_VER2
-# ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405_VER2)
+# if defined(CONFIG_CPCI405AB)
 #  include "fpgadata_cpci405ab.c"
 # else
 #  include "fpgadata_cpci4052.c"
@@ -56,7 +57,7 @@ const unsigned char fpgadata[] =
 #include "../common/fpga.c"
 #include "../common/auto_update.h"
 
-#ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405AB)
 au_image_t au_image[] = {
 	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
 	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@@ -65,7 +66,7 @@ au_image_t au_image[] = {
 	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
 };
 #else
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 au_image_t au_image[] = {
 	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
 	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@@ -91,7 +92,7 @@ int cpci405_version(void);
 int gunzip(void *, int, unsigned char *, unsigned long *);
 void lxt971_no_sleep(void);
 
-int board_early_init_f (void)
+int board_early_init_f(void)
 {
 #ifndef CONFIG_CPCI405_VER2
 	int index, len, i;
@@ -100,18 +101,19 @@ int board_early_init_f (void)
 
 #ifdef FPGA_DEBUG
 	/* set up serial port with default baudrate */
-	(void) get_clocks ();
+	(void)get_clocks();
 	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init ();
+	serial_init();
 	console_init_f();
 #endif
 
 	/*
-	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+	 * First pull fpga-prg pin low,
+	 * to disable fpga logic (on version 2 board)
 	 */
 	out32(GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
-	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output	*/
-	out32(GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output	*/
+	out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
 	out32(GPIO0_OR, 0);		     /* pull prg low		*/
 
 	/*
@@ -124,39 +126,42 @@ int board_early_init_f (void)
 			/* booting FPGA failed */
 #ifndef FPGA_DEBUG
 			/* set up serial port with default baudrate */
-			(void) get_clocks ();
+			(void)get_clocks();
 			gd->baudrate = CONFIG_BAUDRATE;
-			serial_init ();
+			serial_init();
 			console_init_f();
 #endif
 			printf("\nFPGA: Booting failed ");
 			switch (status) {
 			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
 				break;
 			}
 
 			/* display infos on fpgaimage */
 			index = 15;
-			for (i=0; i<4; i++) {
+			for (i = 0; i < 4; i++) {
 				len = fpgadata[index];
-				printf("FPGA: %s\n", &(fpgadata[index+1]));
-				index += len+3;
+				printf("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
 			}
-			putc ('\n');
+			putc('\n');
 			/* delayed reboot */
-			for (i=20; i>0; i--) {
+			for (i = 20; i > 0; i--) {
 				printf("Rebooting in %2d seconds \r",i);
-				for (index=0;index<1000;index++)
+				for (index = 0; index < 1000; index++)
 					udelay(1000);
 			}
-			putc ('\n');
+			putc('\n');
 			do_reset(NULL, 0, 0, NULL);
 		}
 	}
@@ -167,7 +172,7 @@ int board_early_init_f (void)
 	 * IRQ 16    405GP internally generated; active low; level sensitive
 	 * IRQ 17-24 RESERVED
 	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
 	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
@@ -177,7 +182,7 @@ int board_early_init_f (void)
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(uicer, 0x00000000);	/* disable all ints */
 	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
 	if (cpci405_version() == 3) {
 		mtdcr(uicpr, 0xFFFFFF99);	/* set int polarities */
 	} else {
@@ -187,21 +192,20 @@ int board_early_init_f (void)
 	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
 #endif
 	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,
+					 * INT0 highest priority */
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
 int ctermm2(void)
 {
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 	return 0;			/* no, board is cpci405 */
 #else
-	if ((*(unsigned char *)0xf0000400 == 0x00) &&
-	    (*(unsigned char *)0xf0000401 == 0x01))
+	if ((in_8((void*)0xf0000400) == 0x00) &&
+	    (in_8((void*)0xf0000401) == 0x01))
 		return 0;		/* no, board is cpci405 */
 	else
 		return -1;		/* yes, board is cterm-m2 */
@@ -228,8 +232,8 @@ int cpci405_version(void)
 	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
 	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
 	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
-	udelay(1000);			/* wait some time before reading input */
-	value = in_be32((void*)GPIO0_IR) & 0x00180000;	     /* get config bits */
+	udelay(1000); /* wait some time before reading input */
+	value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
 
 	/*
 	 * Restore GPIO settings
@@ -263,7 +267,7 @@ int misc_init_r (void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 	{
 	unsigned char *dst;
 	ulong len = sizeof(fpgadata);
@@ -283,9 +287,10 @@ int misc_init_r (void)
 		mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 
 		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-		if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
-			printf ("GUNZIP ERROR - must RESET board to recover\n");
-			do_reset (NULL, 0, 0, NULL);
+		if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+			   (uchar *)fpgadata, &len) != 0) {
+			printf("GUNZIP ERROR - must RESET board to recover\n");
+			do_reset(NULL, 0, 0, NULL);
 		}
 
 		status = fpga_boot(dst, len);
@@ -293,31 +298,34 @@ int misc_init_r (void)
 			printf("\nFPGA: Booting failed ");
 			switch (status) {
 			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
 				break;
 			}
 
 			/* display infos on fpgaimage */
 			index = 15;
-			for (i=0; i<4; i++) {
+			for (i = 0; i < 4; i++) {
 				len = dst[index];
-				printf("FPGA: %s\n", &(dst[index+1]));
-				index += len+3;
+				printf("FPGA: %s\n", &(dst[index + 1]));
+				index += len + 3;
 			}
-			putc ('\n');
+			putc('\n');
 			/* delayed reboot */
-			for (i=20; i>0; i--) {
-				printf("Rebooting in %2d seconds \r",i);
-				for (index=0;index<1000;index++)
+			for (i = 20; i > 0; i--) {
+				printf("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
 					udelay(1000);
 			}
-			putc ('\n');
+			putc('\n');
 			do_reset(NULL, 0, 0, NULL);
 		}
 
@@ -328,12 +336,12 @@ int misc_init_r (void)
 
 		/* display infos on fpgaimage */
 		index = 15;
-		for (i=0; i<4; i++) {
+		for (i = 0; i < 4; i++) {
 			len = dst[index];
-			printf("%s ", &(dst[index+1]));
-			index += len+3;
+			printf("%s ", &(dst[index + 1]));
+			index += len + 3;
 		}
-		putc ('\n');
+		putc('\n');
 
 		free(dst);
 
@@ -345,68 +353,48 @@ int misc_init_r (void)
 		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 		udelay(1000); /* wait 1ms */
 
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
 		if (cpci405_version() == 3) {
-			volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-			volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
-
 			/*
 			 * Enable outputs in fpga on version 3 board
 			 */
-			*fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
 
 			/*
 			 * Set outputs to 0
 			 */
-			*leds = 0x00;
+			out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
 
 			/*
 			 * Reset external DUART
 			 */
-			*fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_DUART_RESET);
 			udelay(100);
-			*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+				 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
 		}
 #endif
 	}
 	else {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
 		puts("*** CPCI-405 Version 1.x detected!\n");
-		puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI405 instead of CPCI4052)!\n\n");
 	}
 	}
-
 #else /* CONFIG_CPCI405_VER2 */
-
-#if 0 /* test-only: code-plug now not relavant for ip-address any more */
-	/*
-	 * Generate last byte of ip-addr from code-plug @ 0xf0000400
-	 */
-	if (ctermm2()) {
-		char str[32];
-		unsigned char ipbyte = *(unsigned char *)0xf0000400;
-
-		/*
-		 * Only overwrite ip-addr with allowed values
-		 */
-		if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
-			bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
-			sprintf(str, "%ld.%ld.%ld.%ld",
-				(bd->bi_ip_addr & 0xff000000) >> 24,
-				(bd->bi_ip_addr & 0x00ff0000) >> 16,
-				(bd->bi_ip_addr & 0x0000ff00) >> 8,
-				(bd->bi_ip_addr & 0x000000ff));
-			setenv("ipaddr", str);
-		}
-	}
-#endif
-
 	if (cpci405_version() >= 2) {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
 		puts("*** CPCI-405 Board Version 2.x detected!\n");
-		puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI4052 instead of CPCI405)!\n\n");
 	}
-
 #endif /* CONFIG_CPCI405_VER2 */
 
 	/*
@@ -415,46 +403,33 @@ int misc_init_r (void)
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x00001000);
 
-	return (0);
+	return 0;
 }
 
 /*
  * Check Board Identity:
  */
 
-int checkboard (void)
+int checkboard(void)
 {
 #ifndef CONFIG_CPCI405_VER2
 	int index;
 	int len;
 #endif
 	char str[64];
-	int i = getenv_r ("serial#", str, sizeof(str));
+	int i = getenv_r("serial#", str, sizeof(str));
 	unsigned short ver;
 
-	puts ("Board: ");
+	puts("Board: ");
 
-	if (i == -1) {
-		puts ("### No HW ID - assuming CPCI405");
-	} else {
+	if (i == -1)
+		puts("### No HW ID - assuming CPCI405");
+	else
 		puts(str);
-	}
 
 	ver = cpci405_version();
 	printf(" (Ver %d.x, ", ver);
 
-#if 0 /* test-only */
-	if (ver >= 2) {
-		volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
-
-		if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
-			puts ("FLASH Bank B, ");
-		} else {
-			puts ("FLASH Bank A, ");
-		}
-	}
-#endif
-
 	if (ctermm2()) {
 		char str[4];
 
@@ -465,32 +440,31 @@ int checkboard (void)
 		setenv("boardid", str);
 		printf("CTERM-M2 - Id=%s)", str);
 	} else {
-		if (cpci405_host()) {
-			puts ("PCI Host Version)");
-		} else {
-			puts ("PCI Adapter Version)");
-		}
+		if (cpci405_host())
+			puts("PCI Host Version)");
+		else
+			puts("PCI Adapter Version)");
 	}
 
 #ifndef CONFIG_CPCI405_VER2
-	puts ("\nFPGA:	");
+	puts("\nFPGA:	");
 
 	/* display infos on fpgaimage */
 	index = 15;
-	for (i=0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		len = fpgadata[index];
-		printf("%s ", &(fpgadata[index+1]));
-		index += len+3;
+		printf("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
 	}
 #endif
 
-	putc ('\n');
+	putc('\n');
 	return 0;
 }
 
 void reset_phy(void)
 {
-#ifdef CONFIG_LXT971_NO_SLEEP
+#if defined(CONFIG_LXT971_NO_SLEEP)
 
 	/*
 	 * Disable sleep mode in LXT971
@@ -499,25 +473,24 @@ void reset_phy(void)
 #endif
 }
 
-#ifdef CONFIG_CPCI405_VER2
-#ifdef CONFIG_IDE_RESET
-
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
 void ide_set_reset(int on)
 {
-	volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
-	if (on) {		/* assert RESET */
-		*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
-	} else {		/* release RESET */
-		*fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
+	if (on) {	/* assert RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+			 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+	} else {	/* release RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+			 CONFIG_SYS_FPGA_MODE_CF_RESET);
 	}
 }
 
-#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CPCI405_VER2 */
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
 
 #if defined(CONFIG_PCI)
 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
@@ -552,15 +525,44 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in adapter mode.
+	 */
+	if (!cpci405_host()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) | \
+					  CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 
-#ifdef CONFIG_CPCI405AB
+#define ONE_WIRE_SET	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) & \
+					  ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 
-#define ONE_WIRE_CLEAR	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
-			  |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
-			  &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
-			  & CONFIG_SYS_FPGA_MODE_1WIRE)
+#define ONE_WIRE_GET	 (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+					  CONFIG_SYS_FPGA_STATUS)) &  \
+			  CONFIG_SYS_FPGA_MODE_1WIRE)
 
 /*
  * Generate a 1-wire reset, return 1 if no presence detect was found,
@@ -630,7 +632,7 @@ void OWWriteByte(int data)
 {
 	int loop;
 
-	for (loop=0; loop<8; loop++) {
+	for (loop = 0; loop < 8; loop++) {
 		OWWriteBit(data & 0x01);
 		data >>= 1;
 	}
@@ -640,11 +642,10 @@ int OWReadByte(void)
 {
 	int loop, result = 0;
 
-	for (loop=0; loop<8; loop++) {
+	for (loop = 0; loop < 8; loop++) {
 		result >>= 1;
-		if (OWReadBit()) {
+		if (OWReadBit())
 			result |= 0x80;
-		}
 	}
 
 	return result;
@@ -652,7 +653,7 @@ int OWReadByte(void)
 
 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	volatile unsigned short val;
+	unsigned short val;
 	int result;
 	int i;
 	unsigned char ow_id[6];
@@ -662,23 +663,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/*
 	 * Clear 1-wire bit (open drain with pull-up)
 	 */
-	val = *(volatile unsigned short *)0xf0400000;
-	val &= ~0x1000; /* clear 1-wire bit */
-	*(volatile unsigned short *)0xf0400000 = val;
+	val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			      CONFIG_SYS_FPGA_MODE));
+	val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+	out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			 CONFIG_SYS_FPGA_MODE), val);
 
 	result = OWTouchReset();
-	if (result != 0) {
+	if (result != 0)
 		puts("No 1-wire device detected!\n");
-	}
 
 	OWWriteByte(0x33); /* send read rom command */
 	OWReadByte(); /* skip family code ( == 0x01) */
-	for (i=0; i<6; i++) {
+	for (i = 0; i < 6; i++)
 		ow_id[i] = OWReadByte();
-	}
 	ow_crc = OWReadByte(); /* read crc */
 
-	sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+	sprintf(str, "%08X%04X",
+		*(unsigned int *)&ow_id[0],
+		*(unsigned short *)&ow_id[4]);
 	printf("Setting environment variable 'ow_id' to %s\n", str);
 	setenv("ow_id", str);
 
@@ -690,8 +693,8 @@ U_BOOT_CMD(
 	NULL
 	);
 
-#define CONFIG_SYS_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
-#define CONFIG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
 
 /*
  * Write backplane ip-address...
@@ -706,12 +709,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	IPaddr_t ipaddr;
 
 	buf = malloc(CONFIG_ENV_SIZE_2);
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+			(uchar *)buf, CONFIG_ENV_SIZE_2))
 		puts("\nError reading backplane EEPROM!\n");
-	} else {
-		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+	else {
+		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 		if (crc != *(ulong *)buf) {
-			printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+			printf("ERROR: crc mismatch %08lx %08lx\n",
+			       crc, *(ulong *)buf);
 			return -1;
 		}
 
@@ -768,12 +773,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	memset(buf, 0, CONFIG_ENV_SIZE_2);
 	sprintf(str, "bp_ip=%s", argv[1]);
 	strcpy(buf+4, str);
-	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 	*(ulong *)buf = crc;
 
-	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+			 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
 		puts("\nError writing backplane EEPROM!\n");
-	}
 
 	free(buf);
 

board/esd/plu405/plu405.c

@@ -104,6 +104,7 @@ int misc_init_r (void)
 	unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	unsigned char *dst;
+	unsigned char fctr;
 	ulong len = sizeof(fpgadata);
 	int status;
 	int index;
@@ -203,6 +204,15 @@ int misc_init_r (void)
 	out_8(duart0_mcr, 0x08);
 	out_8(duart1_mcr, 0x08);
 
+	/*
+	 * Enable auto RS485 mode in 2nd external uart
+	 */
+	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+	fctr |= 0x08;                       /* enable RS485 mode */
+	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
 	return (0);
 }
 

include/configs/CPCI4052.h

@@ -216,6 +216,8 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is

include/configs/CPCI405AB.h

@@ -92,6 +92,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
 
@@ -212,6 +213,8 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is