8xx, kup4k/kup4x: configuration changes, code cleanup

- nfs-options removed
- hda->sda changed
- mtd parts added
- loadaddress changed
- cmd-line length increased
- lcd stuff removed
- code cleanup (use I/O accessors etc.)

Signed-off-by: Klaus Heydeck <heydeck@kieback-peter.de>

board/kup/common/kup.c

@@ -24,49 +24,61 @@
 #include <common.h>
 #include <mpc8xx.h>
 #include "kup.h"
+#include <asm/io.h>
 
-int misc_init_f (void)
+
+int misc_init_f(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile sysconf8xx_t *siu = &immap->im_siu_conf;
 
-	while (siu->sc_sipend & 0x20000000) {
-		/* printf("waiting for 5V VCC\n"); */
-		;
+	while (in_be32(&siu->sc_sipend) & 0x20000000) {
+		debug("waiting for 5V VCC\n");
 	}
 
 	/* RS232 / RS485 default is RS232 */
-	immap->im_ioport.iop_padat &= ~(PA_RS485);
-	immap->im_ioport.iop_papar &= ~(PA_RS485);
-	immap->im_ioport.iop_paodr &= ~(PA_RS485);
-	immap->im_ioport.iop_padir |= (PA_RS485);
+	clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485);
+	clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485);
+	clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485);
+	setbits_be16(&immap->im_ioport.iop_padir, PA_RS485);
+
+	/* IO Reset min 1 msec */
+	setbits_be16(&immap->im_ioport.iop_padat,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	clrbits_be16(&immap->im_ioport.iop_papar,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	clrbits_be16(&immap->im_ioport.iop_paodr,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	setbits_be16(&immap->im_ioport.iop_padir,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
+	udelay(1000);
+	clrbits_be16(&immap->im_ioport.iop_padat,
+				 (PA_RESET_IO_01 | PA_RESET_IO_02));
 	return (0);
 }
 
-
 #ifdef CONFIG_IDE_LED
-void ide_led (uchar led, uchar status)
+void ide_led(uchar led, uchar status)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* We have one led for both pcmcia slots */
-	if (status) {		/* led on */
-		immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW);
-	} else {
-		immap->im_ioport.iop_padat |= (PA_LED_YELLOW);
-	}
+	if (status)
+		clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW);
+	else
+		setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW);
 }
 #endif
 
-void poweron_key (void)
+void poweron_key(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
-	immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1);
-	immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1);
+	clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1);
+	clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1);
 
-	if (immap->im_ioport.iop_pcdat & (PC_SWITCH1))
-		setenv ("key1", "off");
+	if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1))
+		setenv("key1", "off");
 	else
-		setenv ("key1", "on");
+		setenv("key1", "on");
 }

board/kup/common/kup.h

@@ -24,23 +24,33 @@
 #ifndef __KUP_H
 #define __KUP_H
 
-#define PA_8       0x0080
-#define PA_11      0x0010
-#define PA_12      0x0008
-
-#define PB_14      0x00020000
-#define PB_17      0x00004000
-
-#define PC_9       0x0040
-
-#define PA_RS485                 PA_11   /* SCC1: 0=RS232 1=RS485 */
-#define PA_LED_YELLOW            PA_8
-#define BP_USB_VCC               PB_14   /* VCC for USB devices 0=vcc on, 1=vcc off*/
-#define PB_LCD_PWM	         PB_17	 /* PB 17 */
-#define PC_SWITCH1               PC_9    /* Reboot switch */
-
-extern void poweron_key (void);
-
+#define PA_8	0x0080
+#define PA_9	0x0040
+#define PA_10	0x0020
+#define PA_11	0x0010
+#define PA_12	0x0008
+
+#define PB_14	0x00020000
+#define PB_15	0x00010000
+#define PB_16	0x00008000
+#define PB_17	0x00004000
+
+#define PC_4	0x0800
+#define PC_5	0x0400
+#define PC_9	0x0040
+
+#define PA_RS485	PA_11	/* SCC1: 0=RS232 1=RS485 */
+#define PA_LED_YELLOW	PA_8
+#define PA_RESET_IO_01	PA_9	/* Reset left IO */
+#define PA_RESET_IO_02	PA_10	/* Reset right IO */
+#define PB_PROG_IO_01	PB_15	/* Program left IO */
+#define PB_PROG_IO_02	PB_16	/* Program right IO */
+#define BP_USB_VCC	PB_14	/* VCC for USB devices 0=vcc on, 1=vcc off */
+#define PB_LCD_PWM	PB_17	/* PB 17 */
+#define PC_SWITCH1	PC_9	/* Reboot switch */
+
+
+extern void poweron_key(void);
 extern void load_sernum_ethaddr(void);
 
 #endif	/* __KUP_H */

board/kup/kup4k/kup4k.c

@@ -23,35 +23,19 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <mpc8xx.h>
+#include <hwconfig.h>
+#include <i2c.h>
 #include "../common/kup.h"
-#ifdef CONFIG_KUP4K_LOGO
-   #include "s1d13706.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef DEBUG
-#ifdef  DEBUG
-# define debugk(fmt,args...)    printf(fmt ,##args)
-#else
-# define debugk(fmt,args...)
-#endif
-
-typedef struct {
-	volatile unsigned char *VmemAddr;
-	volatile unsigned char *RegAddr;
-} FB_INFO_S1D13xxx;
+#include <asm/io.h>
 
+static unsigned char swapbyte(unsigned char c);
+static int read_diag(void);
 
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_KUP4K_LOGO
-void lcd_logo(bd_t *bd);
-#endif
-
+DECLARE_GLOBAL_DATA_PTR;
 
-/* ------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
 #define	_NOT_USED_	0xFFFFFFFF
 
@@ -60,7 +44,7 @@ const uint sdram_table[] = {
 	 * Single Read. (Offset 0 in UPMA RAM)
 	 */
 	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
-	0x1FF77C47, /* last */
+	0x1FF77C47,		/* last */
 
 	/*
 	 * SDRAM Initialization (offset 5 in UPMA RAM)
@@ -70,28 +54,28 @@ const uint sdram_table[] = {
 	 * sequence, which is executed by a RUN command.
 	 *
 	 */
-		    0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
 
 	/*
 	 * Burst Read. (Offset 8 in UPMA RAM)
 	 */
 	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
-	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Single Write. (Offset 18 in UPMA RAM)
 	 */
-	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Write. (Offset 20 in UPMA RAM)
 	 */
 	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
-					    _NOT_USED_,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
@@ -99,156 +83,169 @@ const uint sdram_table[] = {
 	 * Refresh  (Offset 30 in UPMA RAM)
 	 */
 	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC84, 0xFFFFFC07, /* last */
-				_NOT_USED_, _NOT_USED_,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Exception. (Offset 3c in UPMA RAM)
 	 */
-	0x7FFFFC07, /* last */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 };
 
-/* ------------------------------------------------------------------------- */
-
+/* ----------------------------------------------------------------------- */
 
 /*
  * Check Board Identity:
  */
 
-int checkboard (void)
+int checkboard(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	uchar *latch,rev,mod;
+	uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
 
 	/*
 	 * Init ChipSelect #4 (CAN + HW-Latch)
 	 */
-	immap->im_memctl.memc_or4 = 0xFFFF8926;
-	immap->im_memctl.memc_br4 = 0x90000401;
-	__asm__ ("eieio");
-	latch=(uchar *)0x90000200;
-	rev = (*latch & 0xF8) >> 3;
-	mod=(*latch & 0x03);
-	printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
-	return (0);
-}
+	out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
+	out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
 
-/* ------------------------------------------------------------------------- */
+	/*
+	 * Init ChipSelect #5 (S1D13768)
+	 */
+	out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
+	out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
 
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size_b0 = 0;
-	long int size_b1 = 0;
-	long int size_b2 = 0;
+	tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
+	rev = (tmp & 0xF8) >> 3;
+	mod = (tmp & 0x07);
 
-	upmconfig (UPMA, (uint *) sdram_table,
-			 sizeof (sdram_table) / sizeof (uint));
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
+	if (read_diag())
+		gd->flags &= ~GD_FLG_SILENT;
+
+	printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
 	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
+	 * TI Application report: Before using the IO as an input,
+	 * a high must be written to the IO first
 	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	pcf = 0xFF;
+	i2c_write(0x21, 0, 0 , &pcf, 1);
+	if (i2c_read(0x21, 0, 0, &pcf, 1)) {
+		puts("n/a\n");
+	} else {
+		ak_rev = (pcf & 0xF8) >> 3;
+		ak_mod = (pcf & 0x07);
+		printf("%d.%d\n", ak_rev, ak_mod);
+	}
+	return 0;
+}
+
+/* ----------------------------------------------------------------------- */
 
-	memctl->memc_mar = 0x00000088;
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size = 0;
+	uchar *latch,rev,mod,tmp;
 
 	/*
-	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
+	 * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
+	 * Rev 1..6 -> 48 MB RAM;   Rev >= 7 -> 96 MB
 	 */
-/*	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	*/
-/*	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	*/
-
-/*	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	*/
-/*	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;	*/
+	out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
+	out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
 
+	latch = (uchar *)0x90000200;
+	tmp = swapbyte(*latch);
+	rev = (tmp & 0xF8) >> 3;
+	mod = (tmp & 0x07);
 
-	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	upmconfig(UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
 
-	udelay (200);
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 
-	/* perform SDRAM initializsation sequence */
+	out_be32(&memctl->memc_mar, 0x00000088);
+	/* no refresh yet */
+	if(rev >= 7) {
+		out_be32(&memctl->memc_mamr,
+				 CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
+	} else {
+		out_be32(&memctl->memc_mamr,
+				 CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
+	}
 
-	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
-	udelay (1);
-	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-	udelay (1000);
-
-#if 0							/* 3 x 8MB */
-	size_b0 = 0x00800000;
-	size_b1 = 0x00800000;
-	size_b2 = 0x00800000;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	udelay (1000);
-	memctl->memc_or1 = 0xFF800A00;
-	memctl->memc_br1 = 0x00000081;
-	memctl->memc_or2 = 0xFF000A00;
-	memctl->memc_br2 = 0x00800081;
-	memctl->memc_or3 = 0xFE000A00;
-	memctl->memc_br3 = 0x01000081;
-#else							/* 3 x 16 MB */
-	size_b0 = 0x01000000;
-	size_b1 = 0x01000000;
-	size_b2 = 0x01000000;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	udelay (1000);
-	memctl->memc_or1 = 0xFF000A00;
-	memctl->memc_br1 = 0x00000081;
-	memctl->memc_or2 = 0xFE000A00;
-	memctl->memc_br2 = 0x01000081;
-	memctl->memc_or3 = 0xFC000A00;
-	memctl->memc_br3 = 0x02000081;
-#endif
+	udelay(200);
 
-	udelay (10000);
+	/* perform SDRAM initializsation sequence */
 
-	return (size_b0 + size_b1 + size_b2);
+	/* SDRAM bank 0 */
+	out_be32(&memctl->memc_mcr, 0x80002105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 1 */
+	out_be32(&memctl->memc_mcr, 0x80004105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 2 */
+	out_be32(&memctl->memc_mcr, 0x80006105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
+	udelay(1000);
+
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+	udelay(1000);
+	if(rev >= 7) {
+		size = 32 * 3 * 1024 * 1024;
+		out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
+		out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
+		out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
+		out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
+		out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
+		out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
+	} else {
+		size = 16 * 3 * 1024 * 1024;
+		out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
+		out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
+		out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
+		out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
+		out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
+		out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
+	}
+	return (size);
 }
 
-/* ------------------------------------------------------------------------- */
+/* ----------------------------------------------------------------------- */
 
-int misc_init_r (void)
+
+int misc_init_r(void)
 {
-#ifdef CONFIG_STATUS_LED
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#endif
-#ifdef CONFIG_KUP4K_LOGO
-	bd_t *bd = gd->bd;
 
-	lcd_logo (bd);
-#endif							/* CONFIG_KUP4K_LOGO */
 #ifdef CONFIG_IDE_LED
 	/* Configure PA8 as output port */
-	immap->im_ioport.iop_padir |= 0x80;
-	immap->im_ioport.iop_paodr |= 0x80;
-	immap->im_ioport.iop_papar &= ~0x80;
-	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
+	setbits_be16(&immap->im_ioport.iop_padir, PA_8);
+	setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
+	clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
+	setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
 #endif
 	load_sernum_ethaddr();
 	setenv("hw","4k");
@@ -256,149 +253,41 @@ int misc_init_r (void)
 	return (0);
 }
 
-#ifdef CONFIG_KUP4K_LOGO
 
-
-void lcd_logo (bd_t * bd)
+static int read_diag(void)
 {
-	FB_INFO_S1D13xxx fb_info;
-	S1D_INDEX s1dReg;
-	S1D_VALUE s1dValue;
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl;
-	ushort i;
-	uchar *fb;
-	int rs, gs, bs;
-	int r = 8, g = 8, b = 4;
-	int r1, g1, b1;
-	int n;
-	char tmp[64];		/* long enough for environment variables */
-	int tft = 0;
-
-	immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
-	immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
-	immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM);	/* set to 0 = enabled */
-	immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
-
-/*----------------------------------------------------------------------------- */
-/* Initialize the chip and the frame buffer driver. */
-/*----------------------------------------------------------------------------- */
-	memctl = &immr->im_memctl;
-
-
-	/*
-	 * Init ChipSelect #5 (S1D13768)
-	 */
-	memctl->memc_or5 = 0xFFC007F0;	/* 4 MB  17 WS or externel TA */
-	memctl->memc_br5 = 0x80080801;	/* Start at 0x80080000 */
-	__asm__ ("eieio");
-
-	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
-	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
-
-	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
-	    || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
-		printf ("Warning:LCD Controller S1D13706 not found\n");
-		setenv ("lcd", "none");
-		return;
-	}
-
-
-	for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
-		s1dReg = aS1DRegs_prelimn[i].Index;
-		s1dValue = aS1DRegs_prelimn[i].Value;
-		debugk ("s13768 reg: %02x value: %02x\n",
-			aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
-		((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
-			s1dValue;
-	}
-
-
-	n = getenv_f("lcd", tmp, sizeof (tmp));
-	if (n > 0) {
-		if (!strcmp ("tft", tmp))
-			tft = 1;
+	int diag;
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4);	/* input */
+	clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4);	/* gpio */
+	setbits_be16(&immr->im_ioport.iop_pcdir, PC_5);	/* output */
+	clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4);	/* gpio */
+	setbits_be16(&immr->im_ioport.iop_pcdat, PC_5);	/* 1 */
+	udelay(500);
+	if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
+		clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
+		udelay(500);
+		if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
+			diag = 0;
 		else
-			tft = 0;
-	}
-#if 0
-	if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
-		tft = 0;
-	else
-		tft = 1;
-#endif
-
-	debugk ("Port=0x%02x -> TFT=%d\n", tft,
-		((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
-
-	/* init controller */
-	if (!tft) {
-		for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
-			s1dReg = aS1DRegs_stn[i].Index;
-			s1dValue = aS1DRegs_stn[i].Value;
-			debugk ("s13768 reg: %02x value: %02x\n",
-				aS1DRegs_stn[i].Index,
-				aS1DRegs_stn[i].Value);
-			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
-				s1dValue;
-		}
-		n = getenv_f("contrast", tmp, sizeof (tmp));
-		((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
-			(n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
-		switch (bd->bi_busfreq) {
-		case 40000000:
-			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
-			break;
-		case 48000000:
-			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
-			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
-			break;
-		default:
-			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
-		case 64000000:
-			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
-			break;
-		}
-		/*   setenv("lcd","stn"); */
+			diag = 1;
 	} else {
-		for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
-			s1dReg = aS1DRegs_tft[i].Index;
-			s1dValue = aS1DRegs_tft[i].Value;
-			debugk ("s13768 reg: %02x value: %02x\n",
-				aS1DRegs_tft[i].Index,
-				aS1DRegs_tft[i].Value);
-			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
-				s1dValue;
-		}
-
-		switch (bd->bi_busfreq) {
-		default:
-			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
-		case 40000000:
-			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
-			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
-			break;
-		}
-		/* setenv("lcd","tft"); */
+		diag = 0;
 	}
+	clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5);	/* input */
+	return (diag);
+}
 
-	/* create and set colormap */
-	rs = 256 / (r - 1);
-	gs = 256 / (g - 1);
-	bs = 256 / (b - 1);
-	for (i = 0; i < 256; i++) {
-		r1 = (rs * ((i / (g * b)) % r)) * 255;
-		g1 = (gs * ((i / b) % g)) * 255;
-		b1 = (bs * ((i) % b)) * 255;
-		debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
-		S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
-				   (b1 >> 4));
-	}
+static unsigned char swapbyte(unsigned char c)
+{
+	unsigned char result = 0;
+	int i = 0;
 
-	/* copy bitmap */
-	fb = (uchar *) (fb_info.VmemAddr);
-	memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
+	for(i = 0; i < 8; ++i) {
+		result = result << 1;
+		result |= (c & 1);
+		c = c >> 1;
+	}
+	return result;
 }
-#endif	/* CONFIG_KUP4K_LOGO */

board/kup/kup4k/s1d13706.h

@@ -1,174 +0,0 @@
-/*---------------------------------------------------------------------------- */
-/* */
-/*  File generated by S1D13706CFG.EXE */
-/* */
-/*  Copyright (c) 2000,2001 Epson Research and Development, Inc. */
-/*  All rights reserved. */
-/* */
-/*---------------------------------------------------------------------------- */
-
-/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
-
-#define S1D_DISPLAY_WIDTH           320
-#define S1D_DISPLAY_HEIGHT          240
-#define S1D_DISPLAY_BPP             8
-#define S1D_DISPLAY_SCANLINE_BYTES  320
-#define S1D_PHYSICAL_VMEM_ADDR      0x800A0000L
-#define S1D_PHYSICAL_VMEM_SIZE      0x14000L
-#define S1D_PHYSICAL_REG_ADDR       0x80080000L
-#define S1D_PHYSICAL_REG_SIZE       0x100
-#define S1D_DISPLAY_PCLK            6250
-#define S1D_PALETTE_SIZE            256
-#define S1D_REGDELAYOFF             0xFFFE
-#define S1D_REGDELAYON              0xFFFF
-
-#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
-{  \
-    ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4);  \
-    ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4);  \
-    ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4);  \
-    ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
-}
-
-#define S1D_READ_PALETTE(p,i,r,g,b)  \
-{  \
-    ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
-    r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)];  \
-    g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)];  \
-    b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)];  \
-}
-
-typedef unsigned short S1D_INDEX;
-typedef unsigned char  S1D_VALUE;
-
-
-typedef struct
-{
-    S1D_INDEX Index;
-    S1D_VALUE Value;
-} S1D_REGS;
-
-
-static S1D_REGS aS1DRegs_prelimn[] =
-{
-    {0x10,0x00},   /* PANEL Type Register */
-    {0xA8,0x00},   /* GPIO Config Register 0 */
-    {0xA9,0x80},   /* GPIO Config Register 1 */
-
-};
-
-static S1D_REGS aS1DRegs_stn[] =
-{
-    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
-    {0x10,0xD0},   /* PANEL Type Register */
-    {0x11,0x00},   /* MOD Rate Register */
-    {0x14,0x27},   /* Horizontal Display Period Register */
-    {0x16,0x00},   /* Horizontal Display Period Start Pos Register 0 */
-    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
-    {0x18,0xF0},   /* Vertical Total Register 0 */
-    {0x19,0x00},   /* Vertical Total Register 1 */
-    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
-    {0x1D,0x00},   /* Vertical Display Period Register 1 */
-    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
-    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
-    {0x20,0x87},   /* Horizontal Sync Pulse Width Register */
-    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
-    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
-    {0x24,0x80},   /* Vertical Sync Pulse Width Register */
-    {0x26,0x01},   /* Vertical Sync Pulse Start Pos Register 0 */
-    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
-    {0x70,0x83},   /* Display Mode Register */
-    {0x71,0x00},   /* Special Effects Register */
-    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
-    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
-    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
-    {0x78,0x50},   /* Main Window Address Offset Register 0 */
-    {0x79,0x00},   /* Main Window Address Offset Register 1 */
-    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
-    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
-    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
-    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
-    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
-    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
-    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
-    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
-    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
-    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
-    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
-    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
-    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
-    {0xA0,0x00},   /* Power Save Config Register */
-    {0xA1,0x00},   /* CPU Access Control Register */
-    {0xA2,0x00},   /* Software Reset Register */
-    {0xA3,0x00},   /* BIG Endian Support Register */
-    {0xA4,0x00},   /* Scratch Pad Register 0 */
-    {0xA5,0x00},   /* Scratch Pad Register 1 */
-    {0xA8,0x01},   /* GPIO Config Register 0 */
-    {0xA9,0x80},   /* GPIO Config Register 1 */
-    {0xAC,0x01},   /* GPIO Status Control Register 0 */
-    {0xAD,0x00},   /* GPIO Status Control Register 1 */
-    {0xB0,0x10},   /* PWM CV Clock Control Register */
-    {0xB1,0x80},   /* PWM CV Clock Config Register */
-    {0xB2,0x00},   /* CV Clock Burst Length Register */
-    {0xAD,0x80},   /* reset seq */
-    {0x70,0x03},
-};
-
-static S1D_REGS aS1DRegs_tft[] =
-{
-    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
-    {0x05,0x42},   /* PCLK Config  Register */
-    {0x10,0x61},   /* PANEL Type Register */
-    {0x11,0x00},   /* MOD Rate Register */
-    {0x12,0x30},   /* Horizontal Total Register */
-    {0x14,0x27},   /* Horizontal Display Period Register */
-    {0x16,0x11},   /* Horizontal Display Period Start Pos Register 0 */
-    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
-    {0x18,0xFA},   /* Vertical Total Register 0 */
-    {0x19,0x00},   /* Vertical Total Register 1 */
-    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
-    {0x1D,0x00},   /* Vertical Display Period Register 1 */
-    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
-    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
-    {0x20,0x07},   /* Horizontal Sync Pulse Width Register */
-    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
-    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
-    {0x24,0x00},   /* Vertical Sync Pulse Width Register */
-    {0x26,0x00},   /* Vertical Sync Pulse Start Pos Register 0 */
-    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
-    {0x70,0x03},   /* Display Mode Register */
-    {0x71,0x00},   /* Special Effects Register */
-    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
-    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
-    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
-    {0x78,0x50},   /* Main Window Address Offset Register 0 */
-    {0x79,0x00},   /* Main Window Address Offset Register 1 */
-    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
-    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
-    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
-    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
-    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
-    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
-    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
-    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
-    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
-    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
-    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
-    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
-    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
-    {0xA0,0x00},   /* Power Save Config Register */
-    {0xA1,0x00},   /* CPU Access Control Register */
-    {0xA2,0x00},   /* Software Reset Register */
-    {0xA3,0x00},   /* BIG Endian Support Register */
-    {0xA4,0x00},   /* Scratch Pad Register 0 */
-    {0xA5,0x00},   /* Scratch Pad Register 1 */
-    {0xA8,0x01},   /* GPIO Config Register 0 */
-    {0xA9,0x80},   /* GPIO Config Register 1 */
-    {0xAC,0x01},   /* GPIO Status Control Register 0 */
-    {0xAD,0x00},   /* GPIO Status Control Register 1 */
-    {0xB0,0x10},   /* PWM CV Clock Control Register */
-    {0xB1,0x80},   /* PWM CV Clock Config Register */
-    {0xB2,0x00},   /* CV Clock Burst Length Register */
-    {0xAD,0x80},   /* reset seq */
-    {0x70,0x03},
-};

board/kup/kup4x/kup4x.c

@@ -26,28 +26,8 @@
 #include <mpc8xx.h>
 #include <post.h>
 #include "../common/kup.h"
-#ifdef CONFIG_KUP4K_LOGO
-/* #include "s1d13706.h" */
-#endif
-
-#define KUP4X_USB
-
-
-typedef struct {
-	volatile unsigned char *VmemAddr;
-	volatile unsigned char *RegAddr;
-} FB_INFO_S1D13xxx;
-
-/* ------------------------------------------------------------------------- */
-
-int usb_init_kup4x (void);
-
+#include <asm/io.h>
 
-#ifdef CONFIG_KUP4K_LOGO
-void lcd_logo (bd_t * bd);
-#endif
-
-/* ------------------------------------------------------------------------- */
 
 #define	_NOT_USED_	0xFFFFFFFF
 
@@ -106,207 +86,116 @@ const uint sdram_table[] = {
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 };
 
-/* ------------------------------------------------------------------------- */
 
 /*
  * Check Board Identity:
  */
 
-int checkboard (void)
+int checkboard(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile uchar *latch;
-	uchar rev, mod;
+	uchar latch, rev, mod;
 
 	/*
 	 * Init ChipSelect #4 (CAN + HW-Latch)
 	 */
-	memctl->memc_or4 = 0xFFFF8926;
-	memctl->memc_br4 = 0x90000401;
-	__asm__ ("eieio");
-	latch = (volatile uchar *) 0x90000200;
-	rev = (*latch & 0xF8) >> 3;
-	mod = (*latch & 0x03);
-	printf ("Board: KUP4X Rev %d.%d\n",rev,mod);
-	return (0);
+	out_be32(&memctl->memc_or4, 0xFFFF8926);
+	out_be32(&memctl->memc_br4, 0x90000401);
+
+	latch = in_8( (unsigned char *) LATCH_ADDR);
+	rev = (latch & 0xF8) >> 3;
+	mod = (latch & 0x03);
+
+	printf("Board: KUP4X Rev %d.%d\n", rev, mod);
+
+	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(int board_type)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size_b0 = 0;
-	long int size_b1 = 0;
-	long int size_b2 = 0;
-	long int size_b3 = 0;
 
-	upmconfig (UPMA, (uint *) sdram_table,
+	upmconfig(UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-	memctl->memc_mar = 0x00000088;
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 
-	/*
-	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-/*	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	*/
-/*	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	*/
+	out_be32(&memctl->memc_mar, 0x00000088);
 
-/*	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	*/
-/*	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;	*/
+	out_be32(&memctl->memc_mamr,
+		 CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */
 
-	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
+	udelay(200);
 
 	/* perform SDRAM initializsation sequence */
 
-	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
-	udelay (1);
-	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mcr = 0x8000C105;	/* SDRAM bank 2 */
-	udelay (1);
-	memctl->memc_mcr = 0x8000C830;	/* SDRAM bank 2 - execute twice */
-	udelay (1);
-	memctl->memc_mcr = 0x8000C106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
-	udelay (1);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-	udelay (1000);
-#if 0				/* 4 x 8MB */
-	size_b0 = 0x00800000;
-	size_b1 = 0x00800000;
-	size_b2 = 0x00800000;
-	size_b3 = 0x00800000;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	udelay (1000);
-	memctl->memc_or1 = 0xFF800A00;
-	memctl->memc_br1 = 0x00000081;
-	memctl->memc_or2 = 0xFF000A00;
-	memctl->memc_br2 = 0x00800081;
-	memctl->memc_or3 = 0xFE000A00;
-	memctl->memc_br3 = 0x01000081;
-	memctl->memc_or6 = 0xFE000A00;
-	memctl->memc_br6 = 0x01800081;
-#else  /* 4 x 16 MB */
-	size_b0 = 0x01000000;
-	size_b1 = 0x01000000;
-	size_b2 = 0x01000000;
-	size_b3 = 0x01000000;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	udelay (1000);
-	memctl->memc_or1 = 0xFF000A00;
-	memctl->memc_br1 = 0x00000081;
-	memctl->memc_or2 = 0xFE000A00;
-	memctl->memc_br2 = 0x01000081;
-	memctl->memc_or3 = 0xFD000A00;
-	memctl->memc_br3 = 0x02000081;
-	memctl->memc_or6 = 0xFC000A00;
-	memctl->memc_br6 = 0x03000081;
-#endif
-	udelay (10000);
-
-	return (size_b0 + size_b1 + size_b2 + size_b3);
+	/* SDRAM bank 0 */
+	out_be32(&memctl->memc_mcr, 0x80002105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 1 */
+	out_be32(&memctl->memc_mcr, 0x80004105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 2 */
+	out_be32(&memctl->memc_mcr, 0x80006105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	/* SDRAM bank 3 */
+	out_be32(&memctl->memc_mcr, 0x8000C105);
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */
+	udelay(1);
+	out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */
+	udelay(1);
+
+	setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
+
+	udelay(1000);
+	/* 4 x 16 MB */
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+	udelay(1000);
+	out_be32(&memctl->memc_or1, 0xFF000A00);
+	out_be32(&memctl->memc_br1, 0x00000081);
+	out_be32(&memctl->memc_or2, 0xFE000A00);
+	out_be32(&memctl->memc_br2, 0x01000081);
+	out_be32(&memctl->memc_or3, 0xFD000A00);
+	out_be32(&memctl->memc_br3, 0x02000081);
+	out_be32(&memctl->memc_or6, 0xFC000A00);
+	out_be32(&memctl->memc_br6, 0x03000081);
+	udelay(10000);
+
+	return (4 * 16 * 1024 * 1024);
 }
 
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-#if 0
-static long int dram_size (long int mamr_value, long int *base,
-			   long int maxsize)
+int misc_init_r(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];		/* to make test non-destructive */
-	unsigned char i = 0;
-
-	memctl->memc_mamr = mamr_value;
-
-	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
-}
-#endif
 
-int misc_init_r (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 #ifdef CONFIG_IDE_LED
 	/* Configure PA8 as output port */
-	immap->im_ioport.iop_padir |= 0x80;
-	immap->im_ioport.iop_paodr |= 0x80;
-	immap->im_ioport.iop_papar &= ~0x80;
-	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
-#endif
-#ifdef KUP4X_USB
-	usb_init_kup4x ();
+	setbits_be16(&immap->im_ioport.iop_padir, PA_8);
+	setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
+	clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
+	setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
 #endif
 	load_sernum_ethaddr();
-	setenv ("hw", "4x");
-	poweron_key ();
-	return (0);
+	setenv("hw", "4x");
+	poweron_key();
+	return 0;
 }

boards.cfg

@@ -160,7 +160,7 @@ TOP860		powerpc	mpc8xx		top860		emk
 kmsupx4		powerpc	mpc8xx		km8xx		keymile
 mgsuvd		powerpc	mpc8xx		km8xx		keymile
 KUP4K		powerpc	mpc8xx		kup4k		kup
-KUP4X		powerpc	mpc8xx		kup4k		kup
+KUP4X		powerpc	mpc8xx		kup4x		kup
 ELPT860		powerpc	mpc8xx		elpt860		LEOX
 CCM		powerpc	mpc8xx		-		siemens
 IAD210		powerpc	mpc8xx		-		siemens

include/configs/KUP4K.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2005
+  * (C) Copyright 2000-2010
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
  *
@@ -42,46 +42,46 @@
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		115200	/* console baudrate		*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
 #define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
-#endif
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
-
 #undef	CONFIG_BOOTARGS
 
-
 #define CONFIG_EXTRA_ENV_SETTINGS						\
-"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
- "run addhw; diskboot 200000 0:1; bootm 200000\0"				\
-"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
- "run addhw; diskboot 200000 2:1; bootm 200000\0"				\
-"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0"			\
+"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;"				\
+ "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0"            \
+"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;"				\
+ "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0"            \
+"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0"	\
+"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw;		\
+ bootm 400000 \0"								\
 "panic_boot=echo No Bootdevice !!! reset\0"					\
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0"		\
 "ramargs=setenv bootargs root=/dev/ram rw\0"					\
-"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}"			\
  ":${netmask}:${hostname}:${netdev}:off\0"					\
-"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
+"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug}	\
+ hw=${hw} key1=${key1} panic=1 mem=${mem}\0"					\
+"console=ttyCPM0,115200\0"							\
 "netdev=eth0\0"									\
-"contrast=55\0"									\
+"contrast=20\0"									\
 "silent=1\0"									\
+"mtdparts=" MTDPARTS_DEFAULT "\0"						\
 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
-"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};"		\
+"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};"		\
  "cp.b 200000 40050000 14000\0"
 
 #define CONFIG_BOOTCOMMAND  \
-    "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
+    "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
 
+#define CONFIG_PREBOOT	"setenv preboot; saveenv"
 
 #define CONFIG_MISC_INIT_R	1
 #define CONFIG_MISC_INIT_F	1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/
 
@@ -98,19 +98,17 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-
 /*
  * enable I2C and select the hardware/software driver
  */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+#undef	CONFIG_HARD_I2C		/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         /* I2C bit-banged		*/
 
-#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CONFIG_SYS_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SLAVE	0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -130,14 +128,12 @@
 #define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
 #endif	/* CONFIG_SOFT_I2C */
 
-
 /*-----------------------------------------------------------------------
  * I2C Configuration
  */
 
-#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
-
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51	/* PCF8563 RTC */
 
 /* List of I2C addresses to be verified by POST */
 
@@ -145,27 +141,13 @@
 			CONFIG_SYS_I2C_RTC_ADDR,	\
 			}
 
-
 #define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
 
 #define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII
 
-#if 0
-#define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
-#endif
-#define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */
-
 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
-#if 1
-/* POST support */
-
-#define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
-				 CONFIG_SYS_POST_RTC	   | \
-				 CONFIG_SYS_POST_I2C)
-#endif
-
 
 /*
  * Command line configuration.
@@ -176,7 +158,9 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_SNTP
 
 #ifdef CONFIG_POST
@@ -191,18 +175,21 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
 #endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x002C00000	/* 4 ... 44 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END		0x005C00000	/* 4 ... 92 MB in DRAM  */
+#define CONFIG_SYS_ALT_MEMTEST 1
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x90000200	/* using latch as scratch register */
 
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
 
@@ -259,19 +246,22 @@
 #define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-/* Address and size of Redundant Environment Sector	*/
-#if 0
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define MTDPARTS_DEFAULT	"mtdparts=40000000.flash:256k(u-boot),"	\
+                                                "64k(env),"		\
+                                                "128k(splash),"		\
+                                                "512k(etc),"		\
+                                                "64k(hw-info)"
+
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#if 1
 #define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
 #define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
-#endif
+#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D		/* 'K&P<CR>' */
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
@@ -286,12 +276,7 @@
  *-----------------------------------------------------------------------
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
-#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
 #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				11-6
@@ -391,7 +376,6 @@
 /* Offset for alternate registers	*/
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
-
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
@@ -416,18 +400,20 @@
 /*
  * FLASH timing:
  */
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV2  | OR_CSNT_SAM | \
+				 OR_SCY_5_CLK | OR_EHTR | OR_BI)
 
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP \
+	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM \
+	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM \
+	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 #define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-
 /*
  * Memory Periodic Timer Prescaler
  *
@@ -475,7 +461,39 @@
 /*
  * MAMR settings for SDRAM
  */
-#define CONFIG_SYS_MAMR 0x80802114
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL 0x68802114
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL 0x68904114
+
+/*
+ * Chip Selects
+ */
+#define CONFIG_SYS_OR0
+#define CONFIG_SYS_BR0
+
+#define CONFIG_SYS_OR1_8COL 0xFF000A00
+#define CONFIG_SYS_BR1_8COL 0x00000081
+#define CONFIG_SYS_OR2_8COL 0xFE000A00
+#define CONFIG_SYS_BR2_8COL 0x01000081
+#define CONFIG_SYS_OR3_8COL 0xFC000A00
+#define CONFIG_SYS_BR3_8COL 0x02000081
+
+#define CONFIG_SYS_OR1_9COL 0xFE000A00
+#define CONFIG_SYS_BR1_9COL 0x00000081
+#define CONFIG_SYS_OR2_9COL 0xFE000A00
+#define CONFIG_SYS_BR2_9COL 0x02000081
+#define CONFIG_SYS_OR3_9COL 0xFE000A00
+#define CONFIG_SYS_BR3_9COL 0x04000081
+
+#define CONFIG_SYS_OR4 0xFFFF8926
+#define CONFIG_SYS_BR4 0x90000401
+
+#define CONFIG_SYS_OR5 0xFFC007F0  /* EPSON: 4 MB  17 WS or externel TA */
+#define CONFIG_SYS_BR5 0x80080801  /* Start at 0x80080000 */
+
+#define LATCH_ADDR 0x90000200
 
 /*
  * Internal Definitions
@@ -487,11 +505,10 @@
 
 
 #define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
-#if 0
-#define CONFIG_AUTOBOOT_PROMPT		\
-	"Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
-#endif
-#define CONFIG_AUTOBOOT_STOP_STR	"." /* easy to stop for now */
-#define CONFIG_SILENT_CONSOLE	1
+#define CONFIG_AUTOBOOT_STOP_STR	"."
+#define CONFIG_SILENT_CONSOLE		1
+#define CONFIG_SYS_DEVICE_NULLDEV	1       /* enble null device            */
+#define CONFIG_VERSION_VARIABLE		1
 
 #endif	/* __CONFIG_H */
+

include/configs/KUP4X.h

@@ -35,23 +35,20 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC859T		1	/* This is a MPC859T CPU		*/
-#define CONFIG_KUP4X		1	/* ...on a KUP4X module			*/
+#define CONFIG_MPC859T		1	/* This is a MPC859T CPU	*/
+#define CONFIG_KUP4X		1	/* ...on a KUP4X module		*/
 
-#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1			*/
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate			*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled			*/
-#else
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second		*/
-#endif
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
 
-#define CONFIG_BOARD_TYPES	1	/* support board types			*/
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
 
-#define CONFIG_SYS_8XX_FACT		8	/* Multiply by 8			*/
-#define CONFIG_SYS_8XX_XIN		16000000	/* 16 MHz in			*/
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_SYS_8XX_FACT		8	/* Multiply by 8	*/
+#define CONFIG_SYS_8XX_XIN		16000000	/* 16 MHz in	*/
 
 
 #define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
@@ -67,9 +64,9 @@
 #define CONFIG_EXTRA_ENV_SETTINGS						\
 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
   "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
-"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
- run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
- usb stop; bootm 200000\0"      \
+"usb_boot=setenv bootargs root=/dev/sda2 ip=off;				\
+ run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;			\
+ usb stop; bootm 200000\0"							\
 "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
 "panic_boot=echo No Bootdevice !!! reset\0"					\
 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
@@ -84,14 +81,14 @@
  "cp.b 200000 40040000 14000\0"
 
 #define CONFIG_BOOTCOMMAND  \
-    "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
+    "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"
 
 
 #define CONFIG_MISC_INIT_R	1
 #define CONFIG_MISC_INIT_F	1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
 
@@ -144,8 +141,8 @@
  * I2C Configuration
  */
 
-#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
 
 
 /* List of I2C addresses to be verified by POST */
@@ -160,22 +157,16 @@
 #define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII
 
-#if 0
-#define CONFIG_ETHADDR                  00:0B:64:80:00:00 /* our OUI from IEEE */
-#endif
 #undef CONFIG_KUP4K_LOGO
 
 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 
-#if 1
 /* POST support */
-
 #define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
 				 CONFIG_SYS_POST_RTC	   | \
 				 CONFIG_SYS_POST_I2C)
-#endif
 
 
 /*
@@ -426,9 +417,12 @@
 #define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
 
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP \
+		(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM \
+		(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM \
+		((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
@@ -443,6 +437,15 @@
 #define CONFIG_SYS_MAMR 0x80802114
 
 
+/*
+ * Chip Selects
+ */
+
+#define CONFIG_SYS_OR4 0xFFFF8926
+#define CONFIG_SYS_BR4 0x90000401
+
+#define LATCH_ADDR 0x90000200
+
 /*
  * Internal Definitions
  *
@@ -453,10 +456,7 @@
 
 
 #define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
-#if 0
-#define CONFIG_AUTOBOOT_PROMPT		\
-	"Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
-#endif
+
 #define CONFIG_AUTOBOOT_STOP_STR	"."	/* easy to stop for now		*/
 #define CONFIG_SILENT_CONSOLE	1