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@@ -259,6 +259,16 @@
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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+/* 32Mbit SRAM @0x30000000 */
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+#define CFG_CS1_START 0x30000000
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+#define CFG_CS1_SIZE 0x00400000
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+#define CFG_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
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+
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+/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
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+#define CFG_CS2_START 0x80000000
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+#define CFG_CS2_SIZE 0x0001000
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+#define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
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+
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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