powerpc/mpc85xx: sparse fixes

fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -182,7 +182,7 @@ static void enable_cpc(void)
 	printf("Corenet Platform Cache: %d KB enabled\n", size);
 }
 
-void invalidate_cpc(void)
+static void invalidate_cpc(void)
 {
 	int i;
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

@@ -489,7 +489,7 @@ static void wait_for_rstdone(unsigned int bank)
 }
 
 
-void __soc_serdes_init(void)
+static void __soc_serdes_init(void)
 {
 	/* Allow for SoC-specific initialization in <SOC>_serdes.c  */
 };

board/freescale/common/ngpixis.c

@@ -237,13 +237,17 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-U_BOOT_CMD(
-	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
-	"Reset the board using the FPGA sequencer",
+#ifdef CONFIG_SYS_LONGHELP
+static char pixis_help_text[] =
 	"- hard reset to default bank\n"
 	"pixis_reset altbank - reset to alternate bank\n"
 #ifdef DEBUG
 	"pixis_reset dump - display the PIXIS registers\n"
 #endif
-	"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
+	"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
+#endif
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer", pixis_help_text
 	);

board/freescale/mpc8568mds/bcsr.c

@@ -25,7 +25,7 @@
 
 #include "bcsr.h"
 
-void enable_8568mds_duart()
+void enable_8568mds_duart(void)
 {
 	volatile uint* duart_mux	= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
 	volatile uint* devices		= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
@@ -36,21 +36,21 @@ void enable_8568mds_duart()
 	bcsr[5] |= 0x01;		/* Enable Duart in BCSR*/
 }
 
-void enable_8568mds_flash_write()
+void enable_8568mds_flash_write(void)
 {
 	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[9] |= 0x01;
 }
 
-void disable_8568mds_flash_write()
+void disable_8568mds_flash_write(void)
 {
 	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[9] &= ~(0x01);
 }
 
-void enable_8568mds_qe_mdio()
+void enable_8568mds_qe_mdio(void)
 {
 	u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 

board/freescale/mpc8569mds/bcsr.c

@@ -25,17 +25,17 @@
 
 #include "bcsr.h"
 
-void enable_8569mds_flash_write()
+void enable_8569mds_flash_write(void)
 {
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void disable_8569mds_flash_write()
+void disable_8569mds_flash_write(void)
 {
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void enable_8569mds_qe_uec()
+void enable_8569mds_qe_uec(void)
 {
 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
@@ -60,7 +60,7 @@ void enable_8569mds_qe_uec()
 #endif
 }
 
-void disable_8569mds_brd_eeprom_write_protect()
+void disable_8569mds_brd_eeprom_write_protect(void)
 {
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
 }