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@@ -79,11 +79,7 @@ skip_check_didle:
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str r1, [r0, #0x0] @ GPIO_CON_OFFSET
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str r1, [r0, #0x0] @ GPIO_CON_OFFSET
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ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
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ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
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-#ifdef CONFIG_ONENAND_IPL
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- orr r1, r1, #(1 << 1) @ 1 * 1-bit
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-#else
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bic r1, r1, #(1 << 1)
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bic r1, r1, #(1 << 1)
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-#endif
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str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
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str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
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/* Don't setup at s5pc100 */
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/* Don't setup at s5pc100 */
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@@ -182,7 +178,6 @@ skip_check_didle:
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/* Do not release retention here for S5PC110 */
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/* Do not release retention here for S5PC110 */
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streq r1, [r0]
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streq r1, [r0]
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-#ifndef CONFIG_ONENAND_IPL
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/* Disable Watchdog */
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/* Disable Watchdog */
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ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
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ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
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ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
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ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
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@@ -193,7 +188,6 @@ skip_check_didle:
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ldrne r0, =S5PC110_SROMC_BASE
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ldrne r0, =S5PC110_SROMC_BASE
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ldr r1, =0x9
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ldr r1, =0x9
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str r1, [r0]
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str r1, [r0]
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-#endif
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/* S5PC100 has 3 groups of interrupt sources */
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/* S5PC100 has 3 groups of interrupt sources */
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ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
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ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
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@@ -207,7 +201,6 @@ skip_check_didle:
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str r3, [r1, #0x14] @ INTENCLEAR
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str r3, [r1, #0x14] @ INTENCLEAR
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str r3, [r2, #0x14] @ INTENCLEAR
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str r3, [r2, #0x14] @ INTENCLEAR
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-#ifndef CONFIG_ONENAND_IPL
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/* Set all interrupts as IRQ */
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/* Set all interrupts as IRQ */
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str r5, [r0, #0xc] @ INTSELECT
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str r5, [r0, #0xc] @ INTSELECT
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str r5, [r1, #0xc] @ INTSELECT
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str r5, [r1, #0xc] @ INTSELECT
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@@ -217,120 +210,12 @@ skip_check_didle:
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str r5, [r0, #0xf00] @ INTADDRESS
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str r5, [r0, #0xf00] @ INTADDRESS
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str r5, [r1, #0xf00] @ INTADDRESS
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str r5, [r1, #0xf00] @ INTADDRESS
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str r5, [r2, #0xf00] @ INTADDRESS
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str r5, [r2, #0xf00] @ INTADDRESS
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-#endif
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-#ifndef CONFIG_ONENAND_IPL
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/* for UART */
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/* for UART */
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bl uart_asm_init
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bl uart_asm_init
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bl internal_ram_init
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bl internal_ram_init
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-#endif
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-
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-#ifdef CONFIG_ONENAND_IPL
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- /* init system clock */
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- bl system_clock_init
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-
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- /* OneNAND Sync Read Support at S5PC110 only
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- * RM[15] : Sync Read
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- * BRWL[14:12] : 7 CLK
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- * BL[11:9] : Continuous
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- * VHF[3] : Very High Frequency Enable (Over 83MHz)
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- * HF[2] : High Frequency Enable (Over 66MHz)
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- * WM[1] : Sync Write
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- */
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- cmp r7, r8
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- ldrne r1, =0xE006
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- ldrne r0, =0xB001E442
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- strneh r1, [r0]
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-
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- /*
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- * GCE[26] : Gated Clock Enable
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- * RPE[17] : Enables Read Prefetch
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- */
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- ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
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- ldrne r0, =0xB0600000
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- strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
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- ldrne r1, =0x1212
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- strne r1, [r0, #0x108]
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-
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- /* Board detection to set proper memory configuration */
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- cmp r7, r8
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- moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
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- movne r9, #2 /* r9 has 2Gib default at s5pc110 */
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-
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- ldr r2, =0xE0200200
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- ldr r4, [r2, #0x48]
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-
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- bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
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- bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
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- bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
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- str r1, [r2, #0x48]
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- /* For write completion */
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- nop
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- nop
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-
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- ldr r3, [r2, #0x44]
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- and r1, r3, #(0x7 << 2)
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- mov r1, r1, lsr #2
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- cmp r1, #0x5
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- moveq r9, #3
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- cmp r1, #0x6
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- moveq r9, #1
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- cmp r1, #0x7
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- moveq r9, #2
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- and r0, r3, #(0x1 << 1)
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- mov r0, r0, lsr #1
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- orr r1, r1, r0, lsl #3
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- cmp r1, #0x8
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- moveq r9, #3
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- and r1, r3, #(0x7 << 2)
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- mov r1, r1, lsr #2
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- and r0, r3, #(0x1 << 7)
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- mov r0, r0, lsr #7
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- orr r1, r1, r0, lsl #3
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- cmp r1, #0x9
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- moveq r9, #3
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- str r4, [r2, #0x48] /* Restore PULLUP configuration */
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-
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- bl mem_ctrl_asm_init
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-
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- /* Wakeup support. Don't know if it's going to be used, untested. */
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- ldreq r0, =S5PC100_RST_STAT
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- ldrne r0, =S5PC110_RST_STAT
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- ldr r1, [r0]
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- biceq r1, r1, #0xfffffff7
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- moveq r2, #(1 << 3)
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- bicne r1, r1, #0xfffeffff
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- movne r2, #(1 << 16)
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- cmp r1, r2
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- bne 1f
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-wakeup:
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- /* turn off L2 cache */
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- bl l2_cache_disable
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-
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- cmp r7, r8
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- ldreq r0, =0xC100
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- ldrne r0, =0xC110
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-
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- /* invalidate L2 cache also */
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- bl invalidate_dcache
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-
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- /* turn on L2 cache */
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- bl l2_cache_enable
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-
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- cmp r7, r8
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- /* Load return address and jump to kernel */
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- ldreq r0, =S5PC100_INFORM0
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- ldrne r0, =S5PC110_INFORM0
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-
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- /* r1 = physical address of s5pc1xx_cpu_resume function */
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- ldr r1, [r0]
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- /* Jump to kernel (sleep-s5pc1xx.S) */
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- mov pc, r1
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- nop
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- nop
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-#else
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cmp r7, r8
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cmp r7, r8
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/* Clear wakeup status register */
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/* Clear wakeup status register */
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ldreq r0, =S5PC100_WAKEUP_STAT
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ldreq r0, =S5PC100_WAKEUP_STAT
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@@ -347,7 +232,6 @@ wakeup:
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orr r1, r1, r2
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orr r1, r1, r2
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str r1, [r0]
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str r1, [r0]
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-#endif
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b 1f
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b 1f
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didle_wakeup:
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didle_wakeup:
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@@ -517,7 +401,6 @@ system_clock_init:
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mov pc, lr
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mov pc, lr
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-#ifndef CONFIG_ONENAND_IPL
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internal_ram_init:
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internal_ram_init:
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ldreq r0, =0xE3800000
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ldreq r0, =0xE3800000
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ldrne r0, =0xF1500000
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ldrne r0, =0xF1500000
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@@ -525,9 +408,7 @@ internal_ram_init:
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str r1, [r0]
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str r1, [r0]
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mov pc, lr
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mov pc, lr
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-#endif
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-#ifndef CONFIG_ONENAND_IPL
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/*
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/*
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* uart_asm_init: Initialize UART's pins
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* uart_asm_init: Initialize UART's pins
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*/
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*/
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@@ -582,4 +463,3 @@ uart_asm_init:
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str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
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str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
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200:
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200:
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mov pc, lr
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mov pc, lr
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-#endif
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