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@@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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0, 2, BOOKE_PAGESZ_256M, 1),
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+#ifndef CONFIG_NAND_SPL
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/* *I*G* - PCI */
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256K, 1),
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0, 6, BOOKE_PAGESZ_256K, 1),
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+#endif
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/* *I*G - NAND */
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/* *I*G - NAND */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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