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ARM: OMAP4: Correct the lpddr2 io settings register value.

To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.

Correcting the above settings here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
SRICHARAN R 13 years ago
parent
7fd5b9bfe4
commit
e423a8f76d
1 changed files with 1 additions and 1 deletions
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  1. 1 1
      arch/arm/include/asm/arch-omap4/omap.h

+ 1 - 1
arch/arm/include/asm/arch-omap4/omap.h
View File 

@@ -112,7 +112,7 @@
 
 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
 
 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
 
 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
 
 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
 
 #define LPDDR2IO_GR10_WD_MASK				(3 << 17)
 
 #define LPDDR2IO_GR10_WD_MASK				(3 << 17)
 
-#define CONTROL_LPDDR2IO_3_VAL		0xA0888C00
 
+#define CONTROL_LPDDR2IO_3_VAL		0xA0888C0F
 
 
 
 /* CONTROL_EFUSE_2 */
 
 /* CONTROL_EFUSE_2 */
 
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
 
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000