ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier

The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.

This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.

Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:

AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz

33MHz async PCI frequency:
PLB = 133:
=>      32 <= 44.3 <= 65        (div = 3)

PLB = 166:
=>      32 <= 55.3 <= 65        (div = 3)

66MHz async PCI frequency:
PLB = 133:
=>      65 <= 66.5 <= 132       (div = 2)

PLB = 166:
=>      65 <= 83 <= 132         (div = 2)

Signed-off-by: Stefan Roese <sr@denx.de>

board/amcc/sequoia/cmd_sequoia.c

@@ -25,6 +25,7 @@
 #include <common.h>
 #include <command.h>
 #include <i2c.h>
+#include <asm/io.h>
 
 /*
  * There are 2 versions of production Sequoia & Rainier platforms.
@@ -200,8 +201,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	/* check CPLD register +5 for PCI 66MHz flag */
-	if (in8(CFG_BCSR_BASE + 5) & 0x01)
-		buf[5] += 0x10;
+	if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
+		/*
+		 * PLB-to-PCI divisor = 3 for 33MHz sync PCI
+		 * instead of 2 for 66MHz systems
+		 */
+		buf[5] |= 0x08;
 
 	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
 		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);