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@@ -132,6 +132,7 @@ reset:
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orr r0, r0, #0xd3
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msr cpsr,r0
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+#if !defined(CONFIG_TEGRA2)
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/*
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* Setup vector:
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* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
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@@ -147,6 +148,7 @@ reset:
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ldr r0, =_start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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#endif
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+#endif /* !Tegra2 */
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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