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+/*
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+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
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+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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+ *
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#ifndef __CONFIG_H
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+#define __CONFIG_H
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+
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+/*
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+ * High Level Configuration Options
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+ */
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+#define CONFIG_E300 1 /* E300 family */
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+#define CONFIG_MPC83xx 1 /* MPC83xx family */
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+#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
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+#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
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+
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+#define CONFIG_MISC_INIT_R
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+
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+/*
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+ * On-board devices
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+ *
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+ * TSEC1 is SoC TSEC
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+ * TSEC2 is VSC switch
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+ */
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+#define CONFIG_TSEC1
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+#define CONFIG_VSC7385_ENET
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+
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+/*
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+ * System Clock Setup
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+ */
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+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
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+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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+
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+/*
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+ * Hardware Reset Configuration Word
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+ * if CLKIN is 66.66MHz, then
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+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
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+ * We choose the A type silicon as default, so the core is 400Mhz.
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+ */
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+#define CONFIG_SYS_HRCW_LOW (\
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+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
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+ HRCWL_SVCOD_DIV_2 |\
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+ HRCWL_CSB_TO_CLKIN_4X1 |\
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+ HRCWL_CORE_TO_CSB_3X1)
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+/*
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+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
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+ * in 8308's HRCWH according to the manual, but original Freescale's
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+ * code has them and I've expirienced some problems using the board
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+ * with BDI3000 attached when I've tried to set these bits to zero
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+ * (UART doesn't work after the 'reset run' command).
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+ */
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+#define CONFIG_SYS_HRCW_HIGH (\
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+ HRCWH_PCI_HOST |\
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+ HRCWH_PCI1_ARBITER_ENABLE |\
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+ HRCWH_CORE_ENABLE |\
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+ HRCWH_FROM_0X00000100 |\
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+ HRCWH_BOOTSEQ_DISABLE |\
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+ HRCWH_SW_WATCHDOG_DISABLE |\
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+ HRCWH_ROM_LOC_LOCAL_16BIT |\
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+ HRCWH_RL_EXT_LEGACY |\
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+ HRCWH_TSEC1M_IN_RGMII |\
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+ HRCWH_TSEC2M_IN_RGMII |\
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+ HRCWH_BIG_ENDIAN)
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+
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+/*
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+ * System IO Config
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+ */
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+#define CONFIG_SYS_SICRH 0x01b7d103
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+#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */
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+
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+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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+
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+/*
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+ * IMMR new address
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+ */
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+#define CONFIG_SYS_IMMR 0xE0000000
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+
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+/*
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+ * SERDES
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+ */
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+#define CONFIG_FSL_SERDES
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+#define CONFIG_FSL_SERDES1 0xe3000
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+
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+/*
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+ * Arbiter Setup
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+ */
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+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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+
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+/*
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+ * DDR Setup
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+ */
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+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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+ | DDRCDR_PZ_LOZ \
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+ | DDRCDR_NZ_LOZ \
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+ | DDRCDR_ODT \
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+ | DDRCDR_Q_DRN)
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+ /* 0x7b880001 */
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+/*
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+ * Manually set up DDR parameters
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+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
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+ */
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+
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+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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+
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+#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
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+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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+ | 0x00010000 /* ODT_WR to CSn */ \
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+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
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+ /* 0x80010102 */
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+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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+ | (0 << TIMING_CFG0_WRT_SHIFT) \
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+ | (0 << TIMING_CFG0_RRT_SHIFT) \
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+ | (0 << TIMING_CFG0_WWT_SHIFT) \
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+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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+ /* 0x00220802 */
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+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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+ | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
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+ | (6 << TIMING_CFG1_REFREC_SHIFT) \
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+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
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+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
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+ /* 0x27256222 */
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+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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+ | (4 << TIMING_CFG2_CPO_SHIFT) \
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+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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+ | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
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+ /* 0x121048c5 */
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+#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
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+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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+ /* 0x03600100 */
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+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
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+ | SDRAM_CFG_32_BE)
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+ /* 0x43080000 */
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+
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+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
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+#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
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+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
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+ /* ODT 150ohm CL=3, AL=1 on SDRAM */
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+#define CONFIG_SYS_DDR_MODE2 0x00000000
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+
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+/*
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+ * Memory test
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+ */
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+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
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+#define CONFIG_SYS_MEMTEST_END 0x07f00000
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+
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+/*
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+ * The reserved memory
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+ */
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+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
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+
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+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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+
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+/*
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+ * Initial RAM Base Address Setup
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+ */
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+#define CONFIG_SYS_INIT_RAM_LOCK 1
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+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
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+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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+#define CONFIG_SYS_GBL_DATA_OFFSET \
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+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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+
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+/*
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+ * Local Bus Configuration & Clock Setup
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+ */
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+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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+#define CONFIG_SYS_LBC_LBCR 0x00040000
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+
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+/*
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+ * FLASH on the Local Bus
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+ */
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+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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+
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+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
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+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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+
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+/* Window base at flash base */
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+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
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+
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+#define CONFIG_SYS_BR0_PRELIM (\
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+ CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
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+ (2 << BR_PS_SHIFT) /* 16 bit port size */ |\
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+ BR_V) /* valid */
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+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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+ | OR_UPM_XAM \
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+ | OR_GPCM_CSNT \
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+ | OR_GPCM_ACS_DIV2 \
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+ | OR_GPCM_XACS \
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+ | OR_GPCM_SCY_15 \
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+ | OR_GPCM_TRLX \
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+ | OR_GPCM_EHTR \
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+ | OR_GPCM_EAD)
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+
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+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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+/* 127 64KB sectors and 8 8KB top sectors per device */
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+#define CONFIG_SYS_MAX_FLASH_SECT 135
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+
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+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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+
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+/*
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+ * NAND Flash on the Local Bus
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+ */
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+#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
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+#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
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+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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+ | BR_PS_8 /* Port Size = 8 bit */ \
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+ | BR_MS_FCM /* MSEL = FCM */ \
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+ | BR_V ) /* valid */
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+#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
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+ | OR_FCM_CSCT \
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+ | OR_FCM_CST \
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+ | OR_FCM_CHT \
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+ | OR_FCM_SCY_1 \
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+ | OR_FCM_TRLX \
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+ | OR_FCM_EHTR )
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+ /* 0xFFFF8396 */
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+
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+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
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+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
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+
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+#ifdef CONFIG_VSC7385_ENET
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+#define CONFIG_TSEC2
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+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
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+#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
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+#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
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+/* Access window base at VSC7385 base */
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+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
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+/* Access window size 128K */
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+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
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+/* The flash address and size of the VSC7385 firmware image */
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+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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+#define CONFIG_VSC7385_IMAGE_SIZE 8192
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+#endif
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+/*
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+ * Serial Port
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+ */
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+#define CONFIG_CONS_INDEX 1
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+#undef CONFIG_SERIAL_SOFTWARE_FIFO
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+#define CONFIG_SYS_NS16550
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+#define CONFIG_SYS_NS16550_SERIAL
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+#define CONFIG_SYS_NS16550_REG_SIZE 1
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+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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+
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+#define CONFIG_SYS_BAUDRATE_TABLE \
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+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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+
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+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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+
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+/* Use the HUSH parser */
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+#define CONFIG_SYS_HUSH_PARSER
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+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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+
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+/* Pass open firmware flat tree */
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+#define CONFIG_OF_LIBFDT 1
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+#define CONFIG_OF_BOARD_SETUP 1
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+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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+
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+/* I2C */
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+#define CONFIG_HARD_I2C /* I2C with hardware support */
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+#define CONFIG_FSL_I2C
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+#define CONFIG_I2C_MULTI_BUS
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+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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+#define CONFIG_SYS_I2C_SLAVE 0x7F
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+#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
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+#define CONFIG_SYS_I2C_OFFSET 0x3000
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+#define CONFIG_SYS_I2C2_OFFSET 0x3100
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+
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+
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+/*
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+ * Board info - revision and where boot from
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+ */
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+#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
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+
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+/*
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+ * Config on-board RTC
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+ */
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+#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
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+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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+
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+/*
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+ * General PCI
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+ * Addresses are mapped 1-1.
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+ */
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+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
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+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
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+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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+#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
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+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
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+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
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+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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+
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+/*
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+ * Fake PCIE2 definitions: there is no PCIE2 on this board but the code
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+ * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
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+ */
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+#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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+#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
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+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
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+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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+#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
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+#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
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+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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+#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
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+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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+
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+#define CONFIG_PCI
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|
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+#define CONFIG_PCIE
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+
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|
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+#define CONFIG_PCI_PNP /* do pci plug-and-play */
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|
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+
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|
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+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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|
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+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
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+
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+/*
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+ * TSEC
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|
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+ */
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|
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+#define CONFIG_NET_MULTI
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+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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+
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+/*
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+ * TSEC ethernet configuration
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|
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+ */
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+#define CONFIG_MII 1 /* MII PHY management */
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+#define CONFIG_TSEC1_NAME "eTSEC0"
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+#define CONFIG_TSEC2_NAME "eTSEC1"
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+#define TSEC1_PHY_ADDR 2
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+#define TSEC2_PHY_ADDR 1
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+#define TSEC1_PHYIDX 0
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+#define TSEC2_PHYIDX 0
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+#define TSEC1_FLAGS TSEC_GIGABIT
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+#define TSEC2_FLAGS TSEC_GIGABIT
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+
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+/* Options are: eTSEC[0-1] */
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+#define CONFIG_ETHPRIME "eTSEC0"
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+
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+/*
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+ * Environment
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+ */
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|
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+#define CONFIG_ENV_IS_IN_FLASH 1
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|
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+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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+ CONFIG_SYS_MONITOR_LEN)
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|
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+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
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|
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+#define CONFIG_ENV_SIZE 0x2000
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|
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+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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+
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+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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|
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+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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+
|
|
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+/*
|
|
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+ * BOOTP options
|
|
|
+ */
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|
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+#define CONFIG_BOOTP_BOOTFILESIZE
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|
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+#define CONFIG_BOOTP_BOOTPATH
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|
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+#define CONFIG_BOOTP_GATEWAY
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|
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+#define CONFIG_BOOTP_HOSTNAME
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|
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+
|
|
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+/*
|
|
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+ * Command line configuration.
|
|
|
+ */
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|
|
+#include <config_cmd_default.h>
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|
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+
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|
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+#define CONFIG_CMD_DATE
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|
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+#define CONFIG_CMD_DHCP
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|
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+#define CONFIG_CMD_I2C
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|
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+#define CONFIG_CMD_MII
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|
|
+#define CONFIG_CMD_NET
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|
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+#define CONFIG_CMD_PCI
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|
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+#define CONFIG_CMD_PING
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|
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+
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|
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+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Miscellaneous configurable options
|
|
|
+ */
|
|
|
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
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|
|
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
|
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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|
|
+
|
|
|
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
|
+
|
|
|
+/* Print Buffer Size */
|
|
|
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
|
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
|
+/* Boot Argument Buffer Size */
|
|
|
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
|
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
|
|
+
|
|
|
+/*
|
|
|
+ * For booting Linux, the board info and command line data
|
|
|
+ * have to be in the first 8 MB of memory, since this is
|
|
|
+ * the maximum mapped by the Linux kernel during initialization.
|
|
|
+ */
|
|
|
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Core HID Setup
|
|
|
+ */
|
|
|
+#define CONFIG_SYS_HID0_INIT 0x000000000
|
|
|
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
|
|
+ HID0_ENABLE_INSTRUCTION_CACHE | \
|
|
|
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
|
|
|
+#define CONFIG_SYS_HID2 HID2_HBE
|
|
|
+
|
|
|
+/*
|
|
|
+ * MMU Setup
|
|
|
+ */
|
|
|
+
|
|
|
+/* DDR: cache cacheable */
|
|
|
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
|
|
|
+ BATL_MEMCOHERENCE)
|
|
|
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
|
|
|
+ BATU_VS | BATU_VP)
|
|
|
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
|
|
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
|
|
+
|
|
|
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
|
|
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
|
|
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
|
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
|
|
|
+ BATU_VP)
|
|
|
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
|
|
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
|
|
+
|
|
|
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
|
|
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
|
|
+ BATL_MEMCOHERENCE)
|
|
|
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
|
|
|
+ BATU_VS | BATU_VP)
|
|
|
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
|
|
+ BATL_CACHEINHIBIT | \
|
|
|
+ BATL_GUARDEDSTORAGE)
|
|
|
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
|
|
+
|
|
|
+/* Stack in dcache: cacheable, no memory coherence */
|
|
|
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
|
|
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
|
|
|
+ BATU_VS | BATU_VP)
|
|
|
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
|
|
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
|
|
+
|
|
|
+/*
|
|
|
+ * Internal Definitions
|
|
|
+ *
|
|
|
+ * Boot Flags
|
|
|
+ */
|
|
|
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
|
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Environment Configuration
|
|
|
+ */
|
|
|
+
|
|
|
+#define CONFIG_ENV_OVERWRITE
|
|
|
+
|
|
|
+#if defined(CONFIG_TSEC_ENET)
|
|
|
+#define CONFIG_HAS_ETH0
|
|
|
+#define CONFIG_HAS_ETH1
|
|
|
+#endif
|
|
|
+
|
|
|
+#define CONFIG_BAUDRATE 115200
|
|
|
+
|
|
|
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
|
|
+
|
|
|
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
|
|
+
|
|
|
+#define xstr(s) str(s)
|
|
|
+#define str(s) #s
|
|
|
+
|
|
|
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
+ "netdev=eth0\0" \
|
|
|
+ "consoledev=ttyS0\0" \
|
|
|
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
|
+ "nfsroot=${serverip}:${rootpath}\0" \
|
|
|
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
|
+ "addip=setenv bootargs ${bootargs} " \
|
|
|
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
|
+ ":${hostname}:${netdev}:off panic=1\0" \
|
|
|
+ "addtty=setenv bootargs ${bootargs}" \
|
|
|
+ " console=${consoledev},${baudrate}\0" \
|
|
|
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
|
|
+ "addmisc=setenv bootargs ${bootargs}\0" \
|
|
|
+ "kernel_addr=FE080000\0" \
|
|
|
+ "fdt_addr=FE280000\0" \
|
|
|
+ "ramdisk_addr=FE290000\0" \
|
|
|
+ "u-boot=mpc8308rdb/u-boot.bin\0" \
|
|
|
+ "kernel_addr_r=1000000\0" \
|
|
|
+ "fdt_addr_r=C00000\0" \
|
|
|
+ "hostname=mpc8308rdb\0" \
|
|
|
+ "bootfile=mpc8308rdb/uImage\0" \
|
|
|
+ "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
|
|
|
+ "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
|
|
|
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
|
|
|
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
|
|
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
|
|
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
|
|
|
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
|
|
+ "tftp ${fdt_addr_r} ${fdtfile};" \
|
|
|
+ "run nfsargs addip addtty addmtd addmisc;" \
|
|
|
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
|
|
+ "bootcmd=run flash_self\0" \
|
|
|
+ "load=tftp ${loadaddr} ${u-boot}\0" \
|
|
|
+ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
|
|
|
+ " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
|
|
|
+ " +${filesize};cp.b ${fileaddr} " \
|
|
|
+ xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
|
|
+ "upd=run load update\0" \
|
|
|
+
|
|
|
+#endif /* __CONFIG_H */
|
Wolfgang Denk