Changes in uboot DDR configuration for MPC8313eRDB

These changes were identified by HighSmith Bill ,Mazzyar and Joseph for
DDR configuration in u-boot code. Some are related to performance, some
affect stability and some correct few basic errors in the current
configuration.

The changes have been tested and found to give better memory latency
figures on MPC8313eRDB.LMBench figures prove it.

The changes are:

- CS0_CONFIG[ AP_n_EN] is changed from 1 to 0
  (this may improve performance for application with many read
  or write to open pages).
- CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to
  001 (activating all the CS when only one is used may cause
  unwanted noise on the system)

- TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on
  Tras=45ns)
- TIMING_CFG_1[REFREC] changed from 21 clks to 18clks.

- TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to
  comply with the 3 ODT clk requirements)
- TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4.
- TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks.

- DDR_SDRAM_MODE[AL]changed from 0 to 1.
- DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks.

- DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510.
- DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500.

The patch is based of git://www.denx.de/git/u-boot-mpc83xx.git
The last commit on this tree was 6775c68683a53c7abc778774641aac6f833a2cbf

Signed-off-by: Poonam Aggrwal-b10812 <b10812@freescale.com>
Cc: Bill HighSmith <Bill.Highsmith@freescale.com>
Cc: Razzaz Mazyar <MRazzaz@freescale.com>
Cc: Josep P J <PJ.Joseph@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

include/configs/MPC8313ERDB.h

@@ -76,10 +76,10 @@
  * seem to have the SPD connected to I2C.
  */
 #define CFG_DDR_SIZE		128		/* MB */
-#define CFG_DDR_CONFIG		( CSCONFIG_EN | CSCONFIG_AP \
-				| 0x00040000 /* TODO */ \
+#define CFG_DDR_CONFIG		( CSCONFIG_EN \
+				| 0x00010000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
-				/* 0x80840102 */
+				/* 0x80010102 */
 
 #define CFG_DDR_TIMING_3	0x00000000
 #define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
@@ -92,25 +92,25 @@
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00220802 */
 #define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
-				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
-				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
+				| (10 << TIMING_CFG1_REFREC_SHIFT ) \
 				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
-				/* 0x3935d322 */
-#define CFG_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
-				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				/* 0x3835a322 */
+#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
-				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
-				/* 0x0f9048ca */ /* P9-45,may need tuning */
-#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
-				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
-				/* 0x03200064 */
+				| ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x129048c6 */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL	( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x05100500 */
 #if defined(CONFIG_DDR_2T_TIMING)
 #define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
@@ -124,9 +124,9 @@
 #endif
 #define CFG_SDRAM_CFG2		0x00401000;
 /* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
-				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
-				/* 0x44400232 */
+#define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44480632 */
 #define CFG_DDR_MODE_2		0x8000C000;
 
 #define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05