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@@ -266,13 +266,13 @@ _start_e500:
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*/
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*/
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lis r3,CFG_INIT_RAM_ADDR@h
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lis r3,CFG_INIT_RAM_ADDR@h
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ori r3,r3,CFG_INIT_RAM_ADDR@l
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ori r3,r3,CFG_INIT_RAM_ADDR@l
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- li r2,512 /* 512*32=16K */
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+ li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
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mtctr r2
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mtctr r2
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li r0,0
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li r0,0
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1:
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1:
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dcbz r0,r3
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dcbz r0,r3
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dcbtls 0,r0,r3
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dcbtls 0,r0,r3
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- addi r3,r3,32
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+ addi r3,r3,CFG_CACHELINE_SIZE
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bdnz 1b
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bdnz 1b
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/* Jump out the last 4K page and continue to 'normal' start */
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/* Jump out the last 4K page and continue to 'normal' start */
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@@ -1066,11 +1066,11 @@ unlock_ram_in_cache:
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/* invalidate the INIT_RAM section */
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/* invalidate the INIT_RAM section */
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lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
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lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
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ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
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ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
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- li r4,512
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+ li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
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mtctr r4
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mtctr r4
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1: icbi r0,r3
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1: icbi r0,r3
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dcbi r0,r3
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dcbi r0,r3
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- addi r3,r3,32
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+ addi r3,r3,CFG_CACHELINE_SIZE
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bdnz 1b
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bdnz 1b
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sync /* Wait for all icbi to complete on bus */
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sync /* Wait for all icbi to complete on bus */
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isync
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isync
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