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@@ -37,14 +37,6 @@ DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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-void fpga_init(void)
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-{
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- /*
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- * Set FPGA regs
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- */
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- out32(CFG_FPGA_BASE, 0xff570cc0);
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-}
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-
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/*
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* Board early initialization function
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*/
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@@ -199,7 +191,12 @@ int board_early_init_f (void)
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*/
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mtsdr(SDR0_SRST, 0);
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- fpga_init();
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+ /*
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+ * Configure FPGA register with PCIe reset
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+ */
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+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
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+ mdelay(50);
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+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
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/* Configure 405EX for NAND usage */
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val = SDR0_CUST0_MUX_NDFC_SEL |
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