This is the first commit for the u-boot zylonite port. The following has be

done so far:

	* created zylonite board dir (based on lubbock)
	* extended some - but not all pxa sources and headers for Intel
	  Monahans support (CONFIG_CPU_MONAHANS)
	* created Makefile zylonite target + MAKEALL entry
	* added some debug nonsense, remove later, grep for mk@tbd

Status: compiles (eldk-4.0), and can be started with BDI, but runs forever
	and doesn't halt at breakpoints. Hmmm...

MAKEALL

@@ -204,7 +204,7 @@ LIST_ARM11="	\
 LIST_pxa="	\
 	adsvix		cerf250		cradle		csb226		\
 	innokom		lubbock		pxa255_idp	wepep250	\
-	xaeniax		xm250		xsengine			\
+	xaeniax		xm250		xsengine	zylonite	\
 "
 
 LIST_ixp="ixdp425"

Makefile

@@ -1633,6 +1633,9 @@ xm250_config	:	unconfig
 xsengine_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa xsengine
 
+zylonite_config :
+	@./mkconfig $(@:_config=) arm pxa zylonite
+
 #########################################################################
 ## ARM1136 Systems
 #########################################################################
@@ -1838,7 +1841,7 @@ clobber:	clean
 		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
 		-print0 \
 		| xargs -0 rm -f
-	rm -f $(OBJS) *.bak tags TAGS
+	rm -f $(OBJS) *.bak tags
 	rm -fr *.*~
 	rm -f u-boot u-boot.map u-boot.hex $(ALL)
 	rm -f tools/crc32.c tools/environment.c tools/env/crc32.c

config.mk

@@ -131,6 +131,10 @@ else
 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
 endif
 
+ifdef WILD_WILD_WEST
+CFLAGS := $(CFLAGS) -Werror
+endif
+
 # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
 # this option have to be placed behind -Wall -- that's why it is here
 ifeq ($(ARCH),nios)

cpu/pxa/cpu.c

@@ -143,6 +143,7 @@ int dcache_status (void)
 	return 0;					/* always off */
 }
 
+#ifndef CONFIG_CPU_MONAHANS
 void set_GPIO_mode(int gpio_mode)
 {
 	int gpio = gpio_mode & GPIO_MD_MASK_NR;
@@ -160,3 +161,5 @@ void set_GPIO_mode(int gpio_mode)
 	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
 	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
 }
+#endif /* CONFIG_CPU_MONAHANS */
+

cpu/pxa/serial.c

@@ -54,7 +54,11 @@ void serial_setbrg (void)
 		hang ();
 
 #ifdef CONFIG_FFUART
+#ifdef CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_22_FFUART;
+#else
 	CKEN |= CKEN6_FFUART;
+#endif /* CONFIG_CPU_MONAHANS */
 
 	FFIER = 0;					/* Disable for now */
 	FFFCR = 0;					/* No fifos enabled */
@@ -68,7 +72,11 @@ void serial_setbrg (void)
 	FFIER = IER_UUE;			/* Enable FFUART */
 
 #elif defined(CONFIG_BTUART)
+#ifdef CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_21_BTUART;
+#else
 	CKEN |= CKEN7_BTUART;
+#endif /*  CONFIG_CPU_MONAHANS */
 
 	BTIER = 0;
 	BTFCR = 0;
@@ -82,7 +90,11 @@ void serial_setbrg (void)
 	BTIER = IER_UUE;			/* Enable BFUART */
 
 #elif defined(CONFIG_STUART)
+#ifdef CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_23_STUART;
+#else
 	CKEN |= CKEN5_STUART;
+#endif /* CONFIG_CPU_MONAHANS */
 
 	STIER = 0;
 	STFCR = 0;

cpu/pxa/start.S

@@ -190,10 +190,10 @@ cpuspeed:	.word	CFG_CPUSPEED
 #endif
 
 
-	/* RS: ???							    */
-	.macro CPWAIT
-	mrc  p15,0,r0,c2,c0,0
-	mov  r0,r0
+	/* takes care the CP15 update has taken place */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
 	sub  pc,pc,#4
 	.endm
 
@@ -201,13 +201,28 @@ cpuspeed:	.word	CFG_CPUSPEED
 cpu_init_crit:
 
 	/* mask all IRQs						    */
+#ifndef CONFIG_CPU_MONAHANS
+	
 	ldr	r0, IC_BASE
 	mov	r1, #0x00
 	str	r1, [r0, #ICMR]
+#else
+	/* Step 1 - Enable CP6 permission */
+        mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
+        orr     r1, r1, #0x40
+	        mcr     p15, 0, r1, c15, c1, 0
+        CPWAIT  r1
+
+        /* Step 2 - Mask ICMR & ICMR2 */
+        mov     r1, #0
+        mcr     p6, 0, r1, c1, c0, 0    @ ICMR
+	mcr     p6, 0, r1, c7, c0, 0    @ ICMR2
+#endif
 
-#if defined(CFG_CPUSPEED)
-
-	/* set clock speed */
+#ifndef CONFIG_CPU_MONAHANS
+#ifdef CFG_CPUSPEED
+	
+	/* set clock speed tbd@mk: required for monahans? */
 	ldr	r0, CC_BASE
 	ldr	r1, cpuspeed
 	str	r1, [r0, #CCCR]
@@ -215,7 +230,10 @@ cpu_init_crit:
 	mcr	p14, 0, r0, c6, c0, 0
 
 setspeed_done:
-#endif
+	
+#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_CPU_MONAHANS */
+	
 
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -227,19 +245,21 @@ setspeed_done:
 	mov	lr,	ip
 
 	/* Memory interfaces are working. Disable MMU and enable I-cache.   */
+	/* mk: hmm, this is not in the monahans docs, leave it now but 
+	 *     check here if it doesn't work :-) */
 
 	ldr	r0, =0x2001		/* enable access to all coproc.	    */
 	mcr	p15, 0, r0, c15, c1, 0
-	CPWAIT
+	CPWAIT r0
 
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write & fill buffers   */
-	CPWAIT
+	CPWAIT r0
 
 	mcr	p15, 0, r0, c7, c7, 0	/* flush Icache, Dcache and BTB	    */
-	CPWAIT
+	CPWAIT r0
 
 	mcr	p15, 0, r0, c8, c7, 0	/* flush instuction and data TLBs   */
-	CPWAIT
+	CPWAIT r0
 
 	/* Enable the Icache						    */
 /*

include/asm-arm/arch-pxa/hardware.h

@@ -8,11 +8,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * Note: This file was taken from linux-2.4.19-rmk4-pxa1
- *
- * - 2003/01/20 implementation specifics activated
- *   Robert Schwebel <r.schwebel@pengutronix.de>
  */
 
 #ifndef __ASM_ARCH_HARDWARE_H
@@ -21,16 +16,6 @@
 #include <linux/config.h>
 #include <asm/mach-types.h>
 
-
-/*
- * These are statically mapped PCMCIA IO space for designs using it as a
- * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
- * The actual PCMCIA code is mapping required IO region at run time.
- */
-#define PCMCIA_IO_0_BASE	0xf6000000
-#define PCMCIA_IO_1_BASE	0xf7000000
-
-
 /*
  * We requires absolute addresses.
  */
@@ -44,22 +29,63 @@
 #define UNCACHED_ADDR		UNCACHED_PHYS_0
 
 /*
- * Intel PXA internal I/O mappings:
+ * Intel PXA2xx internal register mapping:
  *
- * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
- * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
- * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
+ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
+ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
+ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
+ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
+ *
+ * Note that not all PXA2xx chips implement all those addresses, and the
+ * kernel only maps the minimum needed range of this mapping.
+ */
+#ifndef CONFIG_CPU_MONAHANS
+#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
+#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
+#else 
+
+/* There are too many IO area needed to map, so I divide them into 3 areas
+ * 0x40000000 - 0x41ffffff <--> 0xf6000000 - 0xf7ffffff  Devs
  */
+#define io_p2v(x)  ((((x) & 0xfc000000)>>4) + 0xf2000000 + ((x)&0x01ffffff))
+#define io_v2p(x)  (((((x) - 0xf2000000)&0xfc000000)<<4) + ((x)&0x01ffffff))
 
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
+/*
+ * 0x42000000 - 0x421fffff <--> 0xf8000000 - 0xf81fffff  MMC2 & USIM2
+ * 0x43000000 - 0x430fffff <--> 0xf8200000 - 0xf82fffff  Caddo
+ * 0x43100000 - 0x431fffff <--> 0xf8300000 - 0xf83fffff  NAND
+ * 0x44000000 - 0x440fffff <--> 0xf8400000 - 0xf84fffff  LCD
+ * 0x46000000 - 0x460fffff <--> 0xf8800000 - 0xf88fffff  Mini LCD
+ * 0x48100000 - 0x481fffff <--> 0xf8d00000 - 0xf8dfffff  Dynamic Mem Ctl
+ * 0x4a000000 - 0x4a0fffff <--> 0xf9000000 - 0xf90fffff  Static Mem Ctl
+ * 0x4c000000 - 0x4c0fffff <--> 0xf9400000 - 0xf94fffff  USB Host
+ */
 
-#ifndef UBOOT_REG_FIX
-#ifndef __ASSEMBLY__
+#define io_p2v_2(x)	(((((x) - 0x42000000) & 0xff000000) >> 3) + 0xf8000000\
+ 			+ ((x) & 0x001fffff))
+#define io_v2p_2(x)	(((((x) & 0xffe00000) - 0xf8000000) << 3) + 0x42000000\
+				+ (x & 0x001fffff)) 
+/*
+ * 0x50000000 - 0x500fffff <--> 0xfa000000 - 0xfa0fffff  Camera Interface
+ * 0x54000000 - 0x540fffff <--> 0xfa400000 - 0xfa4fffff  2D Graphics Ctrl
+ * 0x54100000 - 0x541fffff <--> 0xfa500000 - 0xfa5fffff  USB Device 2.0 Ctrl
+ * 0x58000000 - 0x580fffff <--> 0xfa800000 - 0xfa8fffff  Internal SRAM Ctrl
+ */
+
+#define io_p2v_3(x)	((((x) & 0xfc000000) >> 4) + 0xf5000000 + \
+				((x) & 0x001fffff)) 
+#define io_v2p_3(x)	(((((x) - 0xf5000000) & 0x0fc00000) << 4) + \
+				((x) & 0x001fffff)) 
+#endif /* CONFIG_CPU_MONAHANS */
 
-#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
-#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
+#ifndef __ASSEMBLY__
 
+#if 0
+# define __REG(x)	(*((volatile u32 *)io_p2v(x)))
+#else
 /*
  * This __REG() version gives the same results as the one above,  except
  * that we are fooling gcc somehow so it generates far better and smaller
@@ -70,62 +96,56 @@
 typedef struct { volatile u32 offset[4096]; } __regbase;
 # define __REGP(x)	((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
 # define __REG(x)	__REGP(io_p2v(x))
-#endif
 
-/* Let's kick gcc's ass again... */
-# define __REG2(x,y)	\
-	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
-				  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+/* __REG_2 is for NAND, LCD etc.
+ * __REG_3 is for Camera Interface, 2D Graphics, U2D etc.*/
+#ifdef CONFIG_CPU_MONAHANS
+#define __REG_2(x)	__REGP(io_p2v_2(x))
+#define __REG_3(x)	__REGP(io_p2v_3(x))
+
+#endif /* CONFIG_CPU_MONAHANS */
+#endif /* if 0 */
+
+/* With indexed regs we don't want to feed the index through io_p2v()
+   especially if it is a variable, otherwise horrible code will result. */
+# define __REG2(x,y)     (*(volatile u32 *)((u32)&__REG(x) + (y)))
 
 # define __PREG(x)	(io_v2p((u32)&(x)))
 
-#else
+#else /* ifndef __ASSEMBLY__ */
 
 # define __REG(x)	io_p2v(x)
 # define __PREG(x)	io_v2p(x)
 
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)	   (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
+#ifdef CONFIG_CPU_MONAHANS
+# define __REG_2(x)	io_p2v(x)
+# define __REG_3(x)	io_p2v(x)
+#endif /* CONFIG_CPU_MONAHANS */
 
-#include "pxa-regs.h"
+#endif /* ifndef __ASSEMBLY__ */
 
 #ifndef __ASSEMBLY__
 
-/*
- * GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * This must be called *before* the corresponding IRQ is registered.
- * Use this instead of directly setting GRER/GFER.
- */
-#define GPIO_FALLING_EDGE	1
-#define GPIO_RISING_EDGE	2
-#define GPIO_BOTH_EDGES		3
-extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
+#ifdef CONFIG_MACH_ZYLONITE
+#include "zylonite.h"
+#endif
 
 /*
  * Handy routine to set GPIO alternate functions
  */
-extern void set_GPIO_mode( int gpio_mode );
+extern void pxa_gpio_mode( int gpio_mode );
 
 /*
- * return current lclk frequency in units of 10kHz
+ * Routine to enable or disable CKEN
  */
-extern unsigned int get_lclk_frequency_10khz(void);
-
-#endif
-
+extern void pxa_set_cken(int clock, int enable);
 
 /*
- * Implementation specifics
+ * return current memory and LCD clock frequency in units of 10kHz
  */
+extern unsigned int get_memclk_frequency_10khz(void);
+extern unsigned int get_lcdclk_frequency_10khz(void);
+#endif /* __ASSEMBLY__ */
 
 #ifdef CONFIG_ARCH_LUBBOCK
 #include "lubbock.h"
@@ -139,6 +159,15 @@ extern unsigned int get_lclk_frequency_10khz(void);
 #include "cerf.h"
 #endif
 
+#if CONFIG_CPU_MONAHANS_L2CACHE
+#define	__cpuc_flush_l2cache_all	xscale_flush_l2cache_all
+extern void __cpuc_flush_l2cache_all(void);
+#define	flush_l2cache_all		__cpuc_flush_l2cache_all
+#else
+#define	__cpuc_flush_l2cache_all()	do {} while (0)
+#define	flush_l2cache_all()		do {} while (0)
+#endif
+
 #ifdef CONFIG_ARCH_CSB226
 #include "csb226.h"
 #endif
@@ -151,4 +180,10 @@ extern unsigned int get_lclk_frequency_10khz(void);
 #include "pleb.h"
 #endif
 
-#endif	/* _ASM_ARCH_HARDWARE_H */
+#ifdef CONFIG_MACH_MAINSTONE
+#include "mainstone.h"
+#endif
+
+#include "pxa-regs.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */

lib_arm/board.c

@@ -38,6 +38,8 @@
  * FIQ Stack: 00ebef7c
  */
 
+#define DEBUG 1
+
 #include <common.h>
 #include <command.h>
 #include <malloc.h>