[ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A

This brings back separate settings for PCIe bus numbers depending on chip
revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa
commit. 440SPe rev. A does NOT work properly with the same settings as for
the rev. B (no devices are seen on the bus during enumeration).

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>

cpu/ppc4xx/440spe_pcie.c

@@ -783,9 +783,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 	/*
 	 * Set bus numbers on our root port
 	 */
-	out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
-	out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
-	out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+	if (ppc440spe_revB()) {
+		out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+		out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+		out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+	} else {
+		out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+		out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
+	}
 
 	/*
 	 * Set up outbound translation to hose->mem_space from PLB