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@@ -46,6 +46,8 @@ enum law_size {
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LAW_SIZE_32G,
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};
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+#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
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+
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#ifdef CONFIG_FSL_CORENET
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enum law_trgt_if {
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LAW_TRGT_IF_PCIE_1 = 0x00,
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@@ -78,6 +80,7 @@ enum law_trgt_if {
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LAW_TRGT_IF_CCSR = 0x08,
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LAW_TRGT_IF_DDR_INTRLV = 0x0b,
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LAW_TRGT_IF_RIO = 0x0c,
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+ LAW_TRGT_IF_RIO_2 = 0x0d,
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LAW_TRGT_IF_DDR = 0x0f,
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LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
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};
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