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@@ -29,6 +29,14 @@
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#define USBCTRL_OTGBASE_OFFSET 0x600
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+#ifdef CONFIG_MX25
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+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
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+#define MX25_USB_CTRL_HSTD_BIT (1<<5)
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+#define MX25_USB_CTRL_USBTE_BIT (1<<4)
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+#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
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+#endif
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+
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+#ifdef CONFIG_MX31
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#define MX31_OTG_SIC_SHIFT 29
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#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
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#define MX31_OTG_PM_BIT (1 << 24)
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@@ -42,12 +50,19 @@
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#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
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#define MX31_H1_PM_BIT (1 << 8)
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#define MX31_H1_DT_BIT (1 << 4)
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+#endif
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static int mxc_set_usbcontrol(int port, unsigned int flags)
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{
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unsigned int v;
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+
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+#ifdef CONFIG_MX25
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+ v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
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+ MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
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+#endif
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+
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#ifdef CONFIG_MX31
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- v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);
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+ v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
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switch (port) {
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case 0: /* OTG port */
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@@ -85,36 +100,38 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
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default:
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return -EINVAL;
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}
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-
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- writel(v, MX31_OTG_BASE_ADDR +
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- USBCTRL_OTGBASE_OFFSET);
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#endif
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- return 0;
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+
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+ writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
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+ return 0;
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}
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int ehci_hcd_init(void)
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{
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- u32 tmp;
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struct usb_ehci *ehci;
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+#ifdef CONFIG_MX31
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+ u32 tmp;
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struct clock_control_regs *sc_regs =
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(struct clock_control_regs *)CCM_BASE;
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tmp = __raw_readl(&sc_regs->ccmr);
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__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
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+#endif
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udelay(80);
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/* Take USB2 */
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- ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR +
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+ ehci = (struct usb_ehci *)(IMX_USB_BASE +
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(0x200 * CONFIG_MXC_USB_PORT));
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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hcor = (struct ehci_hcor *)((uint32_t) hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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setbits_le32(&ehci->usbmode, CM_HOST);
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+#ifdef CONFIG_MX31
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setbits_le32(&ehci->control, USB_EN);
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__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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-
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+#endif
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mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
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udelay(10000);
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