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@@ -297,7 +297,7 @@
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/* 8Mbit SRAM @0x80100000 */
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/* 8Mbit SRAM @0x80100000 */
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#define CFG_CS1_START CFG_SRAM_BASE
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#define CFG_CS1_START CFG_SRAM_BASE
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-#define CFG_CS1_SIZE 0x00100000
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+#define CFG_CS1_SIZE 0x00200000
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#define CFG_CS1_CFG 0x21D00
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#define CFG_CS1_CFG 0x21D00
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/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
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/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
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Peter Pearse