Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

MAKEALL

@@ -376,6 +376,7 @@ LIST_85xx="		\
 	MPC8555CDS	\
 	MPC8560ADS	\
 	MPC8568MDS	\
+	MPC8569MDS	\
 	MPC8572DS	\
 	MPC8572DS_36BIT	\
 	PM854		\

Makefile

@@ -2441,6 +2441,9 @@ MPC8555CDS_config:	unconfig
 MPC8568MDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
 
+MPC8569MDS_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8569mds freescale
+
 MPC8572DS_36BIT_config \
 MPC8572DS_config:       unconfig
 	@mkdir -p $(obj)include

board/freescale/mpc8541cds/mpc8541cds.c

@@ -372,21 +372,21 @@ sdram_init(void)
 	cpu_board_rev = get_cpu_board_revision();
 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
-		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= LSDMR_BSMA1617;
 	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
-		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+		lsdmr_common |= LSDMR_BSMA1516;
 	} else {
 		/*
 		 * Assume something unable to identify itself is
 		 * really old, and likely has lines 16/17 mapped.
 		 */
-		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= LSDMR_BSMA1617;
 	}
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -396,7 +396,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -406,7 +406,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -415,7 +415,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);

board/freescale/mpc8548cds/mpc8548cds.c

@@ -185,12 +185,12 @@ sdram_init(void)
 	 */
 	cpu_board_rev = get_cpu_board_revision();
 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+	lsdmr_common |= LSDMR_BSMA1516;
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -200,7 +200,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -210,7 +210,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -219,7 +219,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);

board/freescale/mpc8555cds/mpc8555cds.c

@@ -371,21 +371,21 @@ sdram_init(void)
 	cpu_board_rev = get_cpu_board_revision();
 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
-		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= LSDMR_BSMA1617;
 	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
-		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+		lsdmr_common |= LSDMR_BSMA1516;
 	} else {
 		/*
 		 * Assume something unable to identify itself is
 		 * really old, and likely has lines 16/17 mapped.
 		 */
-		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= LSDMR_BSMA1617;
 	}
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -395,7 +395,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -405,7 +405,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -414,7 +414,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);

board/freescale/mpc8560ads/mpc8560ads.c

@@ -36,6 +36,7 @@
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <asm/fsl_lbc.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);

board/freescale/mpc8568mds/mpc8568mds.c

@@ -243,12 +243,12 @@ sdram_init(void)
 	 * MPC8568 uses "new" 15-16 style addressing.
 	 */
 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+	lsdmr_common |= LSDMR_BSMA1516;
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -258,7 +258,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -268,7 +268,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -277,7 +277,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);

board/freescale/mpc8569mds/Makefile

@@ -0,0 +1,55 @@
+#
+# Copyright 2004-2009 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= bcsr.o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mpc8569mds/bcsr.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8569mds_flash_write()
+{
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP);
+}
+
+void disable_8569mds_flash_write()
+{
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void enable_8569mds_qe_mdio()
+{
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+}
+
+void disable_8569mds_brd_eeprom_write_protect()
+{
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
+}

board/freescale/mpc8569mds/bcsr.h

@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions*/
+/****************************************/
+/* BCSR defines                         */
+/****************************************/
+#define BCSR6_UPC1_EN		0x80
+#define BCSR6_UPC1_POS_EN	0x40
+#define BCSR6_UPC1_ADDR_EN	0x20
+#define BCSR6_UPC1_DEV2		0x10
+#define BCSR6_SD_ENABLE         0x04
+#define BCSR6_TDM2G_EN		0x02
+#define BCSR6_UCC7_RMII_EN	0x01
+
+#define BCSR7_UCC1_GETH_EN	0x80
+#define BCSR7_UCC1_RGMII_EN	0x40
+#define BCSR7_UCC1_RTBI_EN	0x20
+#define BCSR7_GETHRST_MRVL	0x04
+#define BCSR7_BRD_WRT_PROTECT	0x02
+
+#define BCSR8_UCC2_GETH_EN	0x80
+#define BCSR8_UCC2_RGMII_EN	0x40
+#define BCSR8_UCC2_RTBI_EN	0x20
+#define BCSR8_UEM_MARVEL_RESET	0x02
+
+#define BCSR9_UCC3_GETH_EN	0x80
+#define BCSR9_UCC3_RGMII_EN	0x40
+#define BCSR9_UCC3_RTBI_EN	0x20
+#define BCSR9_UCC3_RMII_EN	0x10
+#define BCSR9_UCC3_UEM_MICREL	0x01
+
+#define BCSR10_UCC4_GETH_EN	0x80
+#define BCSR10_UCC4_RGMII_EN	0x40
+#define BCSR10_UCC4_RTBI_EN	0x20
+
+#define BCSR11_LED0		0x40
+#define BCSR11_LED1		0x20
+#define BCSR11_LED2		0x10
+
+#define BCSR12_UCC6_RMII_EN	0x20
+#define BCSR12_UCC8_RMII_EN	0x20
+
+#define BCSR15_SMII6_DIS	0x08
+#define BCSR15_SMII8_DIS	0x04
+
+#define BCSR16_UPC1_DEV2	0x02
+
+#define BCSR17_FLASH_nWP	0x01
+
+/*BCSR Utils functions*/
+
+void enable_8569mds_flash_write(void);
+void disable_8569mds_flash_write(void);
+void enable_8569mds_qe_mdio(void);
+void disable_8569mds_brd_eeprom_write_protect(void);
+
+#endif	/* __BCSR_H_ */

board/freescale/mpc8569mds/config.mk

@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8569mds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8569=1

board/freescale/mpc8569mds/ddr.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		if (ctrl_num == 0 && i == 1)
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0xff;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 2;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}

board/freescale/mpc8569mds/law.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *2)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *3)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
+ *4.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *4.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *4.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *4.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *4.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8569mds/mpc8569mds.c

@@ -0,0 +1,329 @@
+/*
+ * Copyright 2009 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+phys_size_t fixed_sdram(void);
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* QE_MUX_MDC */
+	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
+
+	/* QE_MUX_MDIO */
+	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
+
+	/* UCC_1_RGMII */
+	{2, 11, 2, 0, 1}, /* CLK12 */
+	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
+	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
+	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
+	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
+	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
+	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
+	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
+	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
+	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
+	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
+	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
+	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
+
+	/* UCC_2_RGMII */
+	{2, 16, 2, 0, 3}, /* CLK17 */
+	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
+	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
+	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
+	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
+	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
+	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
+	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
+	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
+	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
+	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
+	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
+	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	enable_8569mds_flash_write();
+
+#ifdef CONFIG_QE
+	enable_8569mds_qe_mdio();
+#endif
+
+#if CONFIG_SYS_I2C2_OFFSET
+	/* Enable I2C2 signals instead of SD signals */
+	volatile struct ccsr_gur *gur;
+	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
+	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
+	gur->plppar1 |= PLPPAR1_I2C2_VAL;
+	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
+	gur->plpdir1 |= PLPDIR1_I2C2_VAL;
+
+	disable_8569mds_brd_eeprom_write_protect();
+#endif
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: 8569 MDS\n");
+
+	return 0;
+}
+
+phys_size_t
+initdram(int board_type)
+{
+	long dram_size = 0;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	/*
+	 * Work around to stabilize DDR DLL MSYNC_IN.
+	 * Errata DDR9 seems to have been fixed.
+	 * This is now the workaround for Errata DDR11:
+	 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+	 */
+	volatile ccsr_gur_t *gur =
+			(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	out_be32(&gur->ddrdllcr, 0x81000000);
+	udelay(200);
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram();
+#endif
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	uint d_init;
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
+	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
+	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+#if defined (CONFIG_DDR_ECC)
+	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
+	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
+	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
+#endif
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+		udelay(1000);
+	}
+	debug("DDR: memory initialized\n\n");
+	udelay(500);
+#endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
+	if (clkdiv == 16)
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+	else if (clkdiv == 8)
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+	else if (clkdiv == 4)
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+
+	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
+}
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif  /* CONFIG_PCIE1 */
+
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur;
+	uint io_sel;
+	uint host_agent;
+
+	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCIE1
+{
+	volatile ccsr_fsl_pci_t *pci;
+	struct pci_controller *hose;
+	int pcie_ep;
+	struct pci_region *r;
+	int pcie_configured;
+
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+	hose = &pcie1_hose;
+	pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+	r = hose->regions;
+	pcie_configured  = io_sel >= 1;
+
+	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n    PCIE connected to slot as %s (base address %x)",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug (" with errors.  Clearing. Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf ("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE1_MEM_BUS,
+				CONFIG_SYS_PCIE1_MEM_PHYS,
+				CONFIG_SYS_PCIE1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE1_IO_BUS,
+				CONFIG_SYS_PCIE1_IO_PHYS,
+				CONFIG_SYS_PCIE1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr,
+					(int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		printf ("PCIE on bus %02x - %02x\n",
+				hose->first_busno,hose->last_busno);
+
+		first_free_busno=hose->last_busno+1;
+
+	} else {
+		printf ("    PCIE: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+			struct pci_controller *hose);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+#endif
+}
+#endif

board/freescale/mpc8569mds/tlb.c

@@ -0,0 +1,103 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 Initializations */
+	/*
+	 * TLBe 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH (upper half)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
+		      CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 1:	16M	Non-cacheable, guarded
+	 * 0xfe000000	16M	FLASH (lower half)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 2:	256M	Non-cacheable, guarded
+	 * 0xa00000000	256M	PCIe MEM (lower half)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLBe 3:	256M	Non-cacheable, guarded
+	 * 0xb00000000	256M	PCIe MEM (higher half)
+	 */
+	SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
+		      (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLBe 4:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe280_0000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 5:	256K	Non-cacheable, guarded
+	 * 0xf8000000	32K BCSR
+	 * 0xf8008000	32K PIB (CS4)
+	 * 0xf8010000	32K PIB (CS5)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/freescale/mpc8569mds/u-boot.lds

@@ -0,0 +1,143 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) + 0x7f000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec ADDR(.text) + 0x7fffc :
+  {
+    *(.resetvec)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -374,3 +374,12 @@ void board_reset(void)
 	while (1)
 		;
 }
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif

board/sbc8548/sbc8548.c

@@ -184,12 +184,12 @@ sdram_init(void)
 	 * MPC8548 uses "new" 15-16 style addressing.
 	 */
 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+	lsdmr_common |= LSDMR_BSMA1516;
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -199,7 +199,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -209,7 +209,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -218,7 +218,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);

board/sbc8641d/sbc8641d.c

@@ -413,3 +413,12 @@ void board_reset(void)
 	__asm__ __volatile__ ("rfi");
 #endif
 }
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif

common/ddr_spd.c

@@ -59,3 +59,56 @@ ddr2_spd_check(const ddr2_spd_eeprom_t *spd)
 
 	return spd_check(p, spd->spd_rev, spd->cksum);
 }
+
+/*
+ * CRC16 compute for DDR3 SPD
+ * Copied from DDR3 SPD spec.
+ */
+static int
+crc16(char *ptr, int count)
+{
+	int crc, i;
+
+	crc = 0;
+	while (--count >= 0) {
+		crc = crc ^ (int)*ptr++ << 8;
+		for (i = 0; i < 8; ++i)
+			if (crc & 0x8000)
+				crc = crc << 1 ^ 0x1021;
+			else
+				crc = crc << 1;
+	}
+	return crc & 0xffff;
+}
+
+unsigned int
+ddr3_spd_check(const ddr3_spd_eeprom_t *spd)
+{
+	char *p = (char *)spd;
+	int csum16;
+	int len;
+	char crc_lsb;	/* byte 126 */
+	char crc_msb;	/* byte 127 */
+
+	/*
+	 * SPD byte0[7] - CRC coverage
+	 * 0 = CRC covers bytes 0~125
+	 * 1 = CRC covers bytes 0~116
+	 */
+
+	len = !(spd->info_size_crc & 0x80) ? 126 : 117;
+	csum16 = crc16(p, len);
+
+	crc_lsb = (char) (csum16 & 0xff);
+	crc_msb = (char) (csum16 >> 8);
+
+	if (spd->crc[0] == crc_lsb && spd->crc[1] == crc_msb) {
+		return 0;
+	} else {
+		printf("SPD checksum unexpected.\n"
+			"Checksum lsb in SPD = %02X, computed SPD = %02X\n"
+			"Checksum msb in SPD = %02X, computed SPD = %02X\n",
+			spd->crc[0], crc_lsb, spd->crc[1], crc_msb);
+		return 1;
+	}
+}

cpu/mpc85xx/Makefile

@@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
 COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
+COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o
 
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \

cpu/mpc85xx/cpu.c

@@ -61,6 +61,8 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(8567, 8567_E),
 	CPU_TYPE_ENTRY(8568, 8568),
 	CPU_TYPE_ENTRY(8568, 8568_E),
+	CPU_TYPE_ENTRY(8569, 8569),
+	CPU_TYPE_ENTRY(8569, 8569_E),
 	CPU_TYPE_ENTRY(8572, 8572),
 	CPU_TYPE_ENTRY(8572, 8572_E),
 	CPU_TYPE_ENTRY(P2020, P2020),

cpu/mpc85xx/cpu_init.c

@@ -345,6 +345,19 @@ int cpu_init_r(void)
 		asm("msync;isync");
 		puts("enabled\n");
 	}
+#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+
+	/* invalidate the L2 cache */
+	mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
+	while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
+		;
+
+	/* enable the cache */
+	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
+
+	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
+		printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
 #else
 	puts("disabled\n");
 #endif

cpu/mpc85xx/ddr-gen3.c

@@ -98,10 +98,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #endif
 
 	/*
-	 * 200 painful micro-seconds must elapse between
+	 * 500 painful micro-seconds must elapse between
 	 * the DDR clock setup and the DDR config enable.
+	 * DDR2 need 200 us, and DDR3 need 500 us from spec,
+	 * we choose the max, that is 500 us for all of case.
 	 */
-	udelay(200);
+	udelay(500);
 	asm volatile("sync;isync");
 
 	/* Let the controller go */

cpu/mpc85xx/fdt.c

@@ -39,13 +39,8 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 {
 	int off;
 	ulong spin_tbl_addr = get_spin_addr();
-	u32 bootpg, id = get_my_id();
-
-	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-	if ((u64)gd->ram_size > 0xfffff000)
-		bootpg = 0xfffff000;
-	else
-		bootpg = gd->ram_size - 4096;
+	u32 bootpg = determine_mp_bootpg();
+	u32 id = get_my_id();
 
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
@@ -80,7 +75,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 }
 #endif
 
-#ifdef CONFIG_L2_CACHE
+#define ft_fixup_l3cache(x, y)
+
+#if defined(CONFIG_L2_CACHE)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
 {
@@ -157,6 +154,66 @@ static inline void ft_fixup_l2cache(void *blob)
 	fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 	fdt_setprop_cell(blob, off, "cache-level", 2);
 	fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
+
+	/* we dont bother w/L3 since no platform of this type has one */
+}
+#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+static inline void ft_fixup_l2cache(void *blob)
+{
+	int off, l2_off, l3_off = -1;
+	u32 *ph;
+	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+	u32 size, line_size, num_ways, num_sets;
+
+	size = (l2cfg0 & 0x3fff) * 64 * 1024;
+	num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
+	line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
+	num_sets = size / (line_size * num_ways);
+
+	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+
+	while (off != -FDT_ERR_NOTFOUND) {
+		ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
+
+		if (ph == NULL) {
+			debug("no next-level-cache property\n");
+			goto next;
+		}
+
+		l2_off = fdt_node_offset_by_phandle(blob, *ph);
+		if (l2_off < 0) {
+			printf("%s: %s\n", __func__, fdt_strerror(off));
+			goto next;
+		}
+
+		fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
+		fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
+		fdt_setprop_cell(blob, l2_off, "cache-size", size);
+		fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
+		fdt_setprop_cell(blob, l2_off, "cache-level", 2);
+		fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+
+		if (l3_off < 0) {
+			ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
+
+			if (ph == NULL) {
+				debug("no next-level-cache property\n");
+				goto next;
+			}
+			l3_off = *ph;
+		}
+next:
+		off = fdt_node_offset_by_prop_value(blob, off,
+				"device_type", "cpu", 4);
+	}
+	if (l3_off > 0) {
+		l3_off = fdt_node_offset_by_phandle(blob, l3_off);
+		if (l3_off < 0) {
+			printf("%s: %s\n", __func__, fdt_strerror(off));
+			return ;
+		}
+		ft_fixup_l3cache(blob, l3_off);
+	}
 }
 #else
 #define ft_fixup_l2cache(x)

cpu/mpc85xx/mp.c

@@ -38,6 +38,7 @@ int cpu_reset(int nr)
 {
 	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
 	out_be32(&pic->pir, 1 << nr);
+	/* the dummy read works around an errata on early 85xx MP PICs */
 	(void)in_be32(&pic->pir);
 	out_be32(&pic->pir, 0x0);
 
@@ -112,6 +113,15 @@ int cpu_release(int nr, int argc, char *argv[])
 	return 0;
 }
 
+u32 determine_mp_bootpg(void)
+{
+	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
+	if ((u64)gd->ram_size > 0xfffff000)
+		return (0xfffff000);
+
+	return (gd->ram_size - 4096);
+}
+
 ulong get_spin_addr(void)
 {
 	extern ulong __secondary_start_page;
@@ -188,13 +198,7 @@ static void pq3_mp_up(unsigned long bootpg)
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
-	u32 bootpg;
-
-	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-	if ((u64)gd->ram_size > 0xfffff000)
-		bootpg = 0xfffff000;
-	else
-		bootpg = gd->ram_size - 4096;
+	u32 bootpg = determine_mp_bootpg();
 
 	lmb_reserve(lmb, bootpg, 4096);
 }
@@ -203,13 +207,7 @@ void setup_mp(void)
 {
 	extern ulong __secondary_start_page;
 	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg;
-
-	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-	if ((u64)gd->ram_size > 0xfffff000)
-		bootpg = 0xfffff000;
-	else
-		bootpg = gd->ram_size - 4096;
+	u32 bootpg = determine_mp_bootpg();
 
 	memcpy((void *)bootpg, (void *)fixup, 4096);
 	flush_cache(bootpg, 4096);

cpu/mpc85xx/mp.h

@@ -1,10 +1,10 @@
 #ifndef __MPC85XX_MP_H_
 #define __MPC85XX_MP_H_
 
+#include <asm/mp.h>
+
 ulong get_spin_addr(void);
-void setup_mp(void);
 u32 get_my_id(void);
-void cpu_mp_lmb_reserve(struct lmb *lmb);
 
 #define BOOT_ENTRY_ADDR_UPPER	0
 #define BOOT_ENTRY_ADDR_LOWER	1

cpu/mpc85xx/release.S

@@ -76,6 +76,22 @@ __secondary_start_page:
 	slwi	r8,r4,5
 	add	r10,r3,r8
 
+#ifdef CONFIG_BACKSIDE_L2_CACHE
+	/* Enable/invalidate the L2 cache */
+	msync
+	lis	r3,L2CSR0_L2FI@h
+	mtspr	SPRN_L2CSR0,r3
+1:
+	mfspr	r3,SPRN_L2CSR0
+	andis.	r1,r3,L2CSR0_L2FI@h
+	bne	1b
+
+	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
+	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
+	mtspr	SPRN_L2CSR0,r3
+	isync
+#endif
+
 #define EPAPR_MAGIC		(0x45504150)
 #define ENTRY_ADDR_UPPER	0
 #define ENTRY_ADDR_LOWER	4

cpu/mpc85xx/start.S

@@ -161,7 +161,9 @@ _start_e500:
 #if defined(CONFIG_ENABLE_36BIT_PHYS)
 	ori	r0,r0,HID0_ENMAS7@l	/* Enable MAS7 */
 #endif
+#ifndef CONFIG_E500MC
 	ori	r0,r0,HID0_TBEN@l	/* Enable Timebase */
+#endif
 	mtspr	HID0,r0
 
 #ifndef CONFIG_E500MC
@@ -184,6 +186,55 @@ _start_e500:
 	mtspr	DBCR0,r0
 #endif
 
+#ifdef CONFIG_MPC8569
+#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
+#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
+
+	/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
+	 * use address space which is more than 12bits, and it must be done in
+	 * the 4K boot page. So we set this bit here.
+	 */
+
+	/* create a temp mapping TLB0[0] for LBCR  */
+	lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
+	ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
+
+	lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
+
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+	mtspr   MAS0,r6
+	mtspr   MAS1,r7
+	mtspr   MAS2,r8
+	mtspr   MAS3,r9
+	isync
+	msync
+	tlbwe
+
+	/* Set LBCR register */
+	lis     r4,CONFIG_SYS_LBCR_ADDR@h
+	ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
+
+	lis     r5,CONFIG_SYS_LBC_LBCR@h
+	ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
+	stw     r5,0(r4)
+	isync
+
+	/* invalidate this temp TLB */
+	lis	r4,CONFIG_SYS_LBC_ADDR@h
+	ori	r4,r4,CONFIG_SYS_LBC_ADDR@l
+	tlbivax	0,r4
+	isync
+
+#endif /* CONFIG_MPC8569 */
+
 	/* create a temp mapping in AS=1 to the 4M boot window */
 	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l

cpu/mpc86xx/Makefile

@@ -29,26 +29,23 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-SOBJS	= cache.o
 
-ifneq ($(CONFIG_NUM_CPUS),1)
-COBJS-y += mp.o
-SOBJS += release.o
-endif
-COBJS-y	+= traps.o
+SOBJS-y += cache.o
+SOBJS-$(CONFIG_MP) += release.o
+
 COBJS-y	+= cpu.o
 COBJS-y	+= cpu_init.o
-COBJS-y	+= speed.o
-COBJS-y	+= interrupts.o
-
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-
-COBJS-$(CONFIG_MPC8641) += ddr-8641.o
 # 8610 & 8641 are identical w/regards to DDR
 COBJS-$(CONFIG_MPC8610) += ddr-8641.o
+COBJS-$(CONFIG_MPC8641) += ddr-8641.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-y	+= interrupts.o
+COBJS-$(CONFIG_MP) += mp.o
+COBJS-y	+= speed.o
+COBJS-y	+= traps.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(START) $(LIB)

cpu/mpc86xx/cpu_init.c

@@ -31,7 +31,7 @@
 #include <mpc86xx.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
-#include "mp.h"
+#include <asm/mp.h>
 
 void setup_bats(void);
 

cpu/mpc86xx/fdt.c

@@ -9,15 +9,15 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include "mp.h"
+#include <asm/mp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
-#if (CONFIG_NUM_CPUS > 1)
+#ifdef CONFIG_MP
 	int off;
-	u32 bootpg;
+	u32 bootpg = determine_mp_bootpg();
 #endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -48,13 +48,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
-#if (CONFIG_NUM_CPUS > 1)
-	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
-	if (gd->ram_size > 0xfffff000)
-		bootpg = 0xfff00000;
-	else
-		bootpg = gd->ram_size - (1024 * 1024);
-
+#ifdef CONFIG_MP
 	/* Reserve the boot page so OSes dont use it */
 	off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 	if (off < 0)

cpu/mpc86xx/mp.c

@@ -4,20 +4,45 @@
 #include <ioports.h>
 #include <lmb.h>
 #include <asm/io.h>
-#include "mp.h"
+#include <asm/mp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (CONFIG_NUM_CPUS > 1)
-void cpu_mp_lmb_reserve(struct lmb *lmb)
+int cpu_reset(int nr)
+{
+	/* dummy function so common/cmd_mp.c will build
+	 * should be implemented in the future, when cpu_release()
+	 * is supported.  Be aware there may be a similiar bug
+	 * as exists on MPC85xx w/its PIC having a timing window
+	 * associated to resetting the core */
+	return 1;
+}
+
+int cpu_status(int nr)
 {
-	u32 bootpg;
+	/* dummy function so common/cmd_mp.c will build */
+	return 0;
+}
+
+int cpu_release(int nr, int argc, char *argv[])
+{
+	/* dummy function so common/cmd_mp.c will build
+	 * should be implemented in the future */
+	return 1;
+}
 
+u32 determine_mp_bootpg(void)
+{
 	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
 	if ((u64)gd->ram_size > 0xfffff000)
-		bootpg = 0xfff00000;
-	else
-		bootpg = gd->ram_size - (1024 * 1024);
+		return (0xfff00000);
+
+	return (gd->ram_size - (1024 * 1024));
+}
+
+void cpu_mp_lmb_reserve(struct lmb *lmb)
+{
+	u32 bootpg = determine_mp_bootpg();
 
 	/* tell u-boot we stole a page */
 	lmb_reserve(lmb, bootpg, 4096);
@@ -31,18 +56,9 @@ void setup_mp(void)
 {
 	extern ulong __secondary_start_page;
 	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg;
+	u32 bootpg = determine_mp_bootpg();
 	u32 bootpg_va;
 
-	/*
-	 * If we have 4G or more of memory, put the boot page at 4Gb-1M.
-	 * Otherwise, put it at the very end of RAM.
-	 */
-	if (gd->ram_size > 0xfffff000)
-		bootpg = 0xfff00000;
-	else
-		bootpg = gd->ram_size - (1024 * 1024);
-
 	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
 		/* We're not covered by the DDR mapping, set up BAT  */
 		write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
@@ -65,4 +81,3 @@ void setup_mp(void)
 		out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
 			 (bootpg >> 12));
 }
-#endif

cpu/mpc86xx/mp.h

@@ -1,7 +0,0 @@
-#ifndef __MPC86XX_MP_H_
-#define __MPC86XX_MP_H_
-
-void setup_mp(void);
-void cpu_mp_lmb_reserve(struct lmb *lmb);
-
-#endif

cpu/mpc86xx/release.S

@@ -41,7 +41,6 @@
  * Core 0 must copy this to a 1M aligned region and set BPTR
  * to point to it.
  */
-#if (CONFIG_NUM_CPUS > 1)
 	.align 12
 .globl __secondary_start_page
 __secondary_start_page:
@@ -166,4 +165,3 @@ invl2:
 	blr
 
 	/* Never Returns, Running in Linux Now */
-#endif

cpu/mpc8xxx/ddr/Makefile

@@ -18,6 +18,10 @@ COBJS-$(CONFIG_FSL_DDR2)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 
+COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
+				   lc_common_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
+
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 

cpu/mpc8xxx/ddr/ctrl_regs.c

@@ -23,11 +23,18 @@ extern unsigned int picos_to_mclk(unsigned int picos);
  *
  * This should likely be either board or controller specific.
  *
- * Rtt(nominal):
+ * Rtt(nominal) - DDR2:
  *	0 = Rtt disabled
  *	1 = 75 ohm
  *	2 = 150 ohm
  *	3 = 50 ohm
+ * Rtt(nominal) - DDR3:
+ *	0 = Rtt disabled
+ *	1 = 60 ohm
+ *	2 = 120 ohm
+ *	3 = 40 ohm
+ *	4 = 20 ohm
+ *	5 = 30 ohm
  *
  * FIXME: Apparently 8641 needs a value of 2
  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
@@ -53,12 +60,37 @@ static inline int fsl_ddr_get_rtt(void)
 #elif defined(CONFIG_FSL_DDR2)
 	rtt = 3;
 #else
-#error "Need Rtt value for DDR3"
+	rtt = 0;
 #endif
 
 	return rtt;
 }
 
+/*
+ * compute the CAS write latency according to DDR3 spec
+ * CWL = 5 if tCK >= 2.5ns
+ *       6 if 2.5ns > tCK >= 1.875ns
+ *       7 if 1.875ns > tCK >= 1.5ns
+ *       8 if 1.5ns > tCK >= 1.25ns
+ */
+static inline unsigned int compute_cas_write_latency(void)
+{
+	unsigned int cwl;
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+
+	if (mclk_ps >= 2500)
+		cwl = 5;
+	else if (mclk_ps >= 1875)
+		cwl = 6;
+	else if (mclk_ps >= 1500)
+		cwl = 7;
+	else if (mclk_ps >= 1250)
+		cwl = 8;
+	else
+		cwl = 8;
+	return cwl;
+}
+
 /* Chip Select Configuration (CSn_CONFIG) */
 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
@@ -126,7 +158,7 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 
-#if defined(CONFIG_FSL_DDR2)
+#if !defined(CONFIG_FSL_DDR1)
 /*
  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
  *
@@ -150,16 +182,32 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	/* Mode register set cycle time (tMRD). */
 	unsigned char tmrd_mclk;
 
-	/* (tXARD and tXARDS). Empirical? */
-	act_pd_exit_mclk = 2;
-
-	/* XXX:  tXARD = 2, tXARDS = 7 - AL. * Empirical? */
+#if defined(CONFIG_FSL_DDR3)
+	/*
+	 * (tXARD and tXARDS). Empirical?
+	 * The DDR3 spec has not tXARD,
+	 * we use the tXP instead of it.
+	 * tXP=max(3nCK, 7.5ns) for DDR3.
+	 * we use the tXP=6
+	 * spec has not the tAXPD, we use
+	 * tAXPD=8, need design to confirm.
+	 */
+	act_pd_exit_mclk = 6;
 	pre_pd_exit_mclk = 6;
-
-	/* FIXME:  tXP = 2 on Micron 667 MHz DIMM */
 	taxpd_mclk = 8;
-
+	tmrd_mclk = 4;
+#else /* CONFIG_FSL_DDR2 */
+	/*
+	 * (tXARD and tXARDS). Empirical?
+	 * tXARD = 2 for DDR2
+	 * tXP=2
+	 * tAXPD=8
+	 */
+	act_pd_exit_mclk = 2;
+	pre_pd_exit_mclk = 2;
+	taxpd_mclk = 8;
 	tmrd_mclk = 2;
+#endif
 
 	ddr->timing_cfg_0 = (0
 		| ((trwt_mclk & 0x3) << 30)	/* RWT */
@@ -177,7 +225,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 
 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
-			       const common_timing_params_t *common_dimm)
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency)
 {
 	/* Extended Activate to precharge interval (tRAS) */
 	unsigned int ext_acttopre = 0;
@@ -190,6 +239,11 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 		ext_acttopre = 1;
 
 	ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
+
+	/* If the CAS latency more than 8, use the ext mode */
+	if (cas_latency > 8)
+		ext_caslat = 1;
+
 	ddr->timing_cfg_3 = (0
 		| ((ext_acttopre & 0x1) << 24)
 		| ((ext_refrec & 0xF) << 16)
@@ -201,6 +255,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 
 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency)
 {
@@ -246,13 +301,42 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 #elif defined(CONFIG_FSL_DDR2)
 	caslat_ctrl = 2 * cas_latency - 1;
 #else
-#error "Need CAS Latency help for DDR3 in fsl_ddr_sdram.c"
+	/*
+	 * if the CAS latency more than 8 cycle,
+	 * we need set extend bit for it at
+	 * TIMING_CFG_3[EXT_CASLAT]
+	 */
+	if (cas_latency > 8)
+		cas_latency -= 8;
+	caslat_ctrl = 2 * cas_latency - 1;
 #endif
 
 	refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 	wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
+	if (popts->OTF_burst_chop_en)
+		wrrec_mclk += 2;
+
 	acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
+	/*
+	 * JEDEC has min requirement for tRRD
+	 */
+#if defined(CONFIG_FSL_DDR3)
+	if (acttoact_mclk < 4)
+		acttoact_mclk = 4;
+#endif
 	wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
+	/*
+	 * JEDEC has some min requirements for tWTR
+	 */
+#if defined(CONFIG_FSL_DDR2)
+	if (wrtord_mclk < 2)
+		wrtord_mclk = 2;
+#elif defined(CONFIG_FSL_DDR3)
+	if (wrtord_mclk < 4)
+		wrtord_mclk = 4;
+#endif
+	if (popts->OTF_burst_chop_en)
+		wrtord_mclk += 2;
 
 	ddr->timing_cfg_1 = (0
 		| ((pretoact_mclk & 0x0F) << 28)
@@ -302,12 +386,27 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	wr_lat = 0;
 #elif defined(CONFIG_FSL_DDR2)
-	wr_lat = cas_latency + additive_latency - 1;
+	wr_lat = cas_latency - 1;
 #else
-#error "Fix WR_LAT for DDR3"
+	wr_lat = compute_cas_write_latency();
 #endif
 
 	rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
+	/*
+	 * JEDEC has some min requirements for tRTP
+	 */
+#if defined(CONFIG_FSL_DDR2)
+	if (rd_to_pre  < 2)
+		rd_to_pre  = 2;
+#elif defined(CONFIG_FSL_DDR3)
+	if (rd_to_pre < 4)
+		rd_to_pre = 4;
+#endif
+	if (additive_latency)
+		rd_to_pre += additive_latency;
+	if (popts->OTF_burst_chop_en)
+		rd_to_pre += 2; /* according to UM */
+
 	wr_data_delay = popts->write_data_delay;
 	cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 	four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
@@ -316,8 +415,8 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((rd_to_pre & 0x7) << 13)
-		| ((wr_data_delay & 0x7) << 10)
+		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
+		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)
 		| ((four_act & 0x3f) << 0)
 		);
@@ -363,9 +462,19 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 
 	dyn_pwr = popts->dynamic_power;
 	dbw = popts->data_bus_width;
-	/* DDR3 must use 8-beat bursts when using 32-bit bus mode */
-	if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1))
-		eight_be = 1;
+	/* 8-beat burst enable DDR-III case
+	 * we must clear it when use the on-the-fly mode,
+	 * must set it when use the 32-bits bus mode.
+	 */
+	if (sdram_type == SDRAM_TYPE_DDR3) {
+		if (popts->burst_length == DDR_BL8)
+			eight_be = 1;
+		if (popts->burst_length == DDR_OTF)
+			eight_be = 0;
+		if (dbw == 0x1)
+			eight_be = 1;
+	}
+
 	threeT_en = popts->threeT_en;
 	twoT_en = popts->twoT_en;
 	ba_intlv_ctl = popts->ba_intlv_ctl;
@@ -428,8 +537,12 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	 *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 	 *      << DDR_SDRAM_INTERVAL[REFINT]
 	 */
+#if defined(CONFIG_FSL_DDR3)
+	obc_cfg = popts->OTF_burst_chop_en;
+#else
+	obc_cfg = 0;
+#endif
 
-	obc_cfg = 0;	/* Make this configurable? */
 	ap_en = 0;	/* Make this configurable? */
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@ -442,6 +555,9 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	d_init = 0;
 #endif
 
+#if defined(CONFIG_FSL_DDR3)
+	md_en = popts->mirrored_dimm;
+#endif
 	ddr->ddr_sdram_cfg_2 = (0
 		| ((frc_sr & 0x1) << 31)
 		| ((sr_ie & 0x1) << 30)
@@ -464,6 +580,20 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
 	unsigned short esdmode2 = 0;	/* Extended SDRAM mode 2 */
 	unsigned short esdmode3 = 0;	/* Extended SDRAM mode 3 */
 
+#if defined(CONFIG_FSL_DDR3)
+	unsigned int rtt_wr = 2;	/* 120 ohm Rtt_WR */
+	unsigned int srt = 0;	/* self-refresh temerature, normal range */
+	unsigned int asr = 0;	/* auto self-refresh disable */
+	unsigned int cwl = compute_cas_write_latency() - 5;
+	unsigned int pasr = 0;	/* partial array self refresh disable */
+
+	esdmode2 = (0
+		| ((rtt_wr & 0x3) << 9)
+		| ((srt & 0x1) << 7)
+		| ((asr & 0x1) << 6)
+		| ((cwl & 0x7) << 3)
+		| ((pasr & 0x7) << 0));
+#endif
 	ddr->ddr_sdram_mode_2 = (0
 				 | ((esdmode2 & 0xFFFF) << 16)
 				 | ((esdmode3 & 0xFFFF) << 0)
@@ -491,6 +621,139 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 }
 
+#if defined(CONFIG_FSL_DDR3)
+/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
+static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency,
+			       unsigned int additive_latency)
+{
+	unsigned short esdmode;		/* Extended SDRAM mode */
+	unsigned short sdmode;		/* SDRAM mode */
+
+	/* Mode Register - MR1 */
+	unsigned int qoff = 0;		/* Output buffer enable 0=yes, 1=no */
+	unsigned int tdqs_en = 0;	/* TDQS Enable: 0=no, 1=yes */
+	unsigned int rtt;
+	unsigned int wrlvl_en = 0;	/* Write level enable: 0=no, 1=yes */
+	unsigned int al = 0;		/* Posted CAS# additive latency (AL) */
+	unsigned int dic = 1;		/* Output driver impedance, 34ohm */
+	unsigned int dll_en = 0;	/* DLL Enable  0=Enable (Normal),
+						       1=Disable (Test/Debug) */
+
+	/* Mode Register - MR0 */
+	unsigned int dll_on;	/* DLL control for precharge PD, 0=off, 1=on */
+	unsigned int wr;	/* Write Recovery */
+	unsigned int dll_rst;	/* DLL Reset */
+	unsigned int mode;	/* Normal=0 or Test=1 */
+	unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
+	/* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
+	unsigned int bt;
+	unsigned int bl;	/* BL: Burst Length */
+
+	unsigned int wr_mclk;
+
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+
+	rtt = fsl_ddr_get_rtt();
+	if (popts->rtt_override)
+		rtt = popts->rtt_override_value;
+
+	if (additive_latency == (cas_latency - 1))
+		al = 1;
+	if (additive_latency == (cas_latency - 2))
+		al = 2;
+
+	/*
+	 * The esdmode value will also be used for writing
+	 * MR1 during write leveling for DDR3, although the
+	 * bits specifically related to the write leveling
+	 * scheme will be handled automatically by the DDR
+	 * controller. so we set the wrlvl_en = 0 here.
+	 */
+	esdmode = (0
+		| ((qoff & 0x1) << 12)
+		| ((tdqs_en & 0x1) << 11)
+		| ((rtt & 0x4) << 9)   /* rtt field is split */
+		| ((wrlvl_en & 0x1) << 7)
+		| ((rtt & 0x2) << 6)   /* rtt field is split */
+		| ((dic & 0x2) << 5)   /* DIC field is split */
+		| ((al & 0x3) << 3)
+		| ((rtt & 0x1) << 2)   /* rtt field is split */
+		| ((dic & 0x1) << 1)   /* DIC field is split */
+		| ((dll_en & 0x1) << 0)
+		);
+
+	/*
+	 * DLL control for precharge PD
+	 * 0=slow exit DLL off (tXPDLL)
+	 * 1=fast exit DLL on (tXP)
+	 */
+	dll_on = 1;
+	wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
+	if (wr_mclk >= 12)
+		wr = 6;
+	else if (wr_mclk >= 9)
+		wr = 5;
+	else
+		wr = wr_mclk - 4;
+	dll_rst = 0;	/* dll no reset */
+	mode = 0;	/* normal mode */
+
+	/* look up table to get the cas latency bits */
+	if (cas_latency >= 5 && cas_latency <= 11) {
+		unsigned char cas_latency_table[7] = {
+			0x2,	/* 5 clocks */
+			0x4,	/* 6 clocks */
+			0x6,	/* 7 clocks */
+			0x8,	/* 8 clocks */
+			0xa,	/* 9 clocks */
+			0xc,	/* 10 clocks */
+			0xe	/* 11 clocks */
+		};
+		caslat = cas_latency_table[cas_latency - 5];
+	}
+	bt = 0;	/* Nibble sequential */
+
+	switch (popts->burst_length) {
+	case DDR_BL8:
+		bl = 0;
+		break;
+	case DDR_OTF:
+		bl = 1;
+		break;
+	case DDR_BC4:
+		bl = 2;
+		break;
+	default:
+		printf("Error: invalid burst length of %u specified. "
+			" Defaulting to on-the-fly BC4 or BL8 beats.\n",
+			popts->burst_length);
+		bl = 1;
+		break;
+	}
+
+	sdmode = (0
+		  | ((dll_on & 0x1) << 12)
+		  | ((wr & 0x7) << 9)
+		  | ((dll_rst & 0x1) << 8)
+		  | ((mode & 0x1) << 7)
+		  | (((caslat >> 1) & 0x7) << 4)
+		  | ((bt & 0x1) << 3)
+		  | ((bl & 0x3) << 0)
+		  );
+
+	ddr->ddr_sdram_mode = (0
+			       | ((esdmode & 0xFFFF) << 16)
+			       | ((sdmode & 0xFFFF) << 0)
+			       );
+
+	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
+}
+
+#else /* !CONFIG_FSL_DDR3 */
+
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
@@ -567,8 +830,6 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	wr = 0;       /* Historical */
 #elif defined(CONFIG_FSL_DDR2)
 	wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
-#else
-#error "Write tWR_auto for DDR3"
 #endif
 	dll_res = 0;
 	mode = 0;
@@ -587,16 +848,14 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	}
 #elif defined(CONFIG_FSL_DDR2)
 	caslat = cas_latency;
-#else
-#error "Fix the mode CAS Latency for DDR3"
 #endif
 	bt = 0;
 
 	switch (popts->burst_length) {
-	case 4:
+	case DDR_BL4:
 		bl = 2;
 		break;
-	case 8:
+	case DDR_BL8:
 		bl = 3;
 		break;
 	default:
@@ -624,7 +883,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 			       );
 	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 }
-
+#endif
 
 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
@@ -678,6 +937,12 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 	unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
 	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 
+#if defined(CONFIG_FSL_DDR3)
+	/* We need set BL/2 + 4 for BC4 or OTF */
+	rrt = 4;	/* BL/2 + 4 clocks */
+	wwt = 4;	/* BL/2 + 4 clocks */
+	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
+#endif
 	ddr->timing_cfg_4 = (0
 			     | ((rwt & 0xf) << 28)
 			     | ((wrt & 0xf) << 24)
@@ -696,6 +961,13 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
 	unsigned int wodt_on = 0;	/* Write to ODT on */
 	unsigned int wodt_off = 0;	/* Write to ODT off */
 
+#if defined(CONFIG_FSL_DDR3)
+	rodt_on = 3;	/*  2 clocks */
+	rodt_off = 4;	/*  4 clocks */
+	wodt_on = 2;	/*  1 clocks */
+	wodt_off = 4;	/*  4 clocks */
+#endif
+
 	ddr->timing_cfg_5 = (0
 			     | ((rodt_on & 0x1f) << 24)
 			     | ((rodt_off & 0x7) << 20)
@@ -706,15 +978,20 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
 }
 
 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
-static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
 {
-	unsigned int zq_en = 0;	/* ZQ Calibration Enable */
 	unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
 	/* Normal Operation Full Calibration Time (tZQoper) */
 	unsigned int zqoper = 0;
 	/* Normal Operation Short Calibration Time (tZQCS) */
 	unsigned int zqcs = 0;
 
+	if (zq_en) {
+		zqinit = 9;	/* 512 clocks */
+		zqoper = 8;	/* 256 clocks */
+		zqcs = 6;	/* 64 clocks */
+	}
+
 	ddr->ddr_zq_cntl = (0
 			    | ((zq_en & 0x1) << 31)
 			    | ((zqinit & 0xF) << 24)
@@ -724,9 +1001,9 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr)
 }
 
 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
-static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
+			       unsigned int wrlvl_en)
 {
-	unsigned int wrlvl_en = 0; /* Write Leveling Enable */
 	/*
 	 * First DQS pulse rising edge after margining mode
 	 * is programmed (tWL_MRD)
@@ -743,6 +1020,34 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
 	/* WRLVL_START: Write leveling start time */
 	unsigned int wrlvl_start = 0;
 
+	/* suggest enable write leveling for DDR3 due to fly-by topology */
+	if (wrlvl_en) {
+		/* tWL_MRD min = 40 nCK, we set it 64 */
+		wrlvl_mrd = 0x6;
+		/* tWL_ODTEN 128 */
+		wrlvl_odten = 0x7;
+		/* tWL_DQSEN min = 25 nCK, we set it 32 */
+		wrlvl_dqsen = 0x5;
+		/*
+		 * Write leveling sample time at least need 14 clocks
+		 * due to tWLO = 9, we set it 15 clocks
+		 */
+		wrlvl_smpl = 0xf;
+		/*
+		 * Write leveling repetition time
+		 * at least tWLO + 6 clocks clocks
+		 * we set it 32
+		 */
+		wrlvl_wlr = 0x5;
+		/*
+		 * Write leveling start time
+		 * The value use for the DQS_ADJUST for the first sample
+		 * when write leveling is enabled.
+		 * we set it 1 clock delay
+		 */
+		wrlvl_start = 0x8;
+	}
+
 	ddr->ddr_wrlvl_cntl = (0
 			       | ((wrlvl_en & 0x1) << 31)
 			       | ((wrlvl_mrd & 0x7) << 24)
@@ -861,6 +1166,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	unsigned int cas_latency;
 	unsigned int additive_latency;
 	unsigned int sr_it;
+	unsigned int zq_en;
+	unsigned int wrlvl_en;
 
 	memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
 
@@ -885,6 +1192,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	sr_it = (popts->auto_self_refresh_en)
 		? popts->sr_it
 		: 0;
+	/* ZQ calibration */
+	zq_en = (popts->zq_en) ? 1 : 0;
+	/* write leveling */
+	wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
 
 	/* Chip Select Memory Bounds (CSn_BNDS) */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
@@ -1019,12 +1330,12 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 		set_csn_config_2(i, ddr);
 	}
 
-#if defined(CONFIG_FSL_DDR2)
+#if !defined(CONFIG_FSL_DDR1)
 	set_timing_cfg_0(ddr);
 #endif
 
-	set_timing_cfg_3(ddr, common_dimm);
-	set_timing_cfg_1(ddr, common_dimm, cas_latency);
+	set_timing_cfg_3(ddr, common_dimm, cas_latency);
+	set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
 	set_timing_cfg_2(ddr, popts, common_dimm,
 				cas_latency, additive_latency);
 
@@ -1042,8 +1353,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_timing_cfg_4(ddr);
 	set_timing_cfg_5(ddr);
 
-	set_ddr_zq_cntl(ddr);
-	set_ddr_wrlvl_cntl(ddr);
+	set_ddr_zq_cntl(ddr, zq_en);
+	set_ddr_wrlvl_cntl(ddr, wrlvl_en);
 
 	set_ddr_pd_cntl(ddr);
 	set_ddr_sr_cntr(ddr, sr_it);

cpu/mpc8xxx/ddr/ddr3_dimm_params.c

@@ -0,0 +1,314 @@
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *	Dave Liu <daveliu@freescale.com>
+ *
+ * calculate the organization and timing parameter
+ * from ddr3 spd, please refer to the spec
+ * JEDEC standard No.21-C 4_01_02_11R18.pdf
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#include "ddr.h"
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * each rank size =
+ * sdram capacity(bit) / 8 * primary bus width / sdram width
+ *
+ * where: sdram capacity  = spd byte4[3:0]
+ *        primary bus width = spd byte8[2:0]
+ *        sdram width = spd byte7[2:0]
+ *
+ * SPD byte4 - sdram density and banks
+ *	bit[3:0]	size(bit)	size(byte)
+ *	0000		256Mb		32MB
+ *	0001		512Mb		64MB
+ *	0010		1Gb		128MB
+ *	0011		2Gb		256MB
+ *	0100		4Gb		512MB
+ *	0101		8Gb		1GB
+ *	0110		16Gb		2GB
+ *
+ * SPD byte8 - module memory bus width
+ * 	bit[2:0]	primary bus width
+ *	000		8bits
+ * 	001		16bits
+ * 	010		32bits
+ * 	011		64bits
+ *
+ * SPD byte7 - module organiztion
+ * 	bit[2:0]	sdram device width
+ * 	000		4bits
+ * 	001		8bits
+ * 	010		16bits
+ * 	011		32bits
+ *
+ */
+static phys_size_t
+compute_ranksize(const ddr3_spd_eeprom_t *spd)
+{
+	phys_size_t bsize;
+
+	int nbit_sdram_cap_bsize = 0;
+	int nbit_primary_bus_width = 0;
+	int nbit_sdram_width = 0;
+
+	if ((spd->density_banks & 0xf) < 7)
+		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
+	if ((spd->bus_width & 0x7) < 4)
+		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
+	if ((spd->organization & 0x7) < 4)
+		nbit_sdram_width = (spd->organization & 0x7) + 2;
+
+	bsize = 1 << (nbit_sdram_cap_bsize - 3
+		    + nbit_primary_bus_width - nbit_sdram_width);
+
+	debug("DDR: DDR III rank density = 0x%08x\n", bsize);
+
+	return bsize;
+}
+
+/*
+ * ddr_compute_dimm_parameters for DDR3 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_t structure pointed by pdimm.
+ *
+ */
+unsigned int
+ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
+			     dimm_params_t *pdimm,
+			     unsigned int dimm_number)
+{
+	unsigned int retval;
+	unsigned int mtb_ps;
+
+	if (spd->mem_type) {
+		if (spd->mem_type != SPD_MEMTYPE_DDR3) {
+			printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
+			return 1;
+		}
+	} else {
+		memset(pdimm, 0, sizeof(dimm_params_t));
+		return 1;
+	}
+
+	retval = ddr3_spd_check(spd);
+	if (retval) {
+		printf("DIMM %u: failed checksum\n", dimm_number);
+		return 2;
+	}
+
+	/*
+	 * The part name in ASCII in the SPD EEPROM is not null terminated.
+	 * Guarantee null termination here by presetting all bytes to 0
+	 * and copying the part name in ASCII from the SPD onto it
+	 */
+	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+	/* DIMM organization parameters */
+	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
+	pdimm->rank_density = compute_ranksize(spd);
+	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
+	if ((spd->bus_width >> 3) & 0x3)
+		pdimm->ec_sdram_width = 8;
+	else
+		pdimm->ec_sdram_width = 0;
+	pdimm->data_width = pdimm->primary_sdram_width
+			  + pdimm->ec_sdram_width;
+
+	switch (spd->module_type & 0xf) {
+	case 0x01:	/* RDIMM */
+	case 0x05:	/* Mini-RDIMM */
+		pdimm->registered_dimm = 1; /* register buffered */
+		break;
+
+	case 0x02:	/* UDIMM */
+	case 0x03:	/* SO-DIMM */
+	case 0x04:	/* Micro-DIMM */
+	case 0x06:	/* Mini-UDIMM */
+		pdimm->registered_dimm = 0;	/* unbuffered */
+		break;
+
+	default:
+		printf("unknown dimm_type 0x%02X\n", spd->module_type);
+		return 1;
+	}
+
+	/* SDRAM device parameters */
+	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
+	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
+	pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
+
+	/*
+	 * The SPD spec has not the ECC bit,
+	 * We consider the DIMM as ECC capability
+	 * when the extension bus exist
+	 */
+	if (pdimm->ec_sdram_width)
+		pdimm->edc_config = 0x02;
+	else
+		pdimm->edc_config = 0x00;
+
+	/*
+	 * The SPD spec has not the burst length byte
+	 * but DDR3 spec has nature BL8 and BC4,
+	 * BL8 -bit3, BC4 -bit2
+	 */
+	pdimm->burst_lengths_bitmask = 0x0c;
+	pdimm->row_density = __ilog2(pdimm->rank_density);
+
+	/* MTB - medium timebase
+	 * The unit in the SPD spec is ns,
+	 * We convert it to ps.
+	 * eg: MTB = 0.125ns (125ps)
+	 */
+	mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
+	pdimm->mtb_ps = mtb_ps;
+
+	/*
+	 * sdram minimum cycle time
+	 * we assume the MTB is 0.125ns
+	 * eg:
+	 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
+	 *        =12 MTB (1.5ns) ->DDR3-1333
+	 *        =10 MTB (1.25ns) ->DDR3-1600
+	 */
+	pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps;
+
+	/*
+	 * CAS latency supported
+	 * bit4 - CL4
+	 * bit5 - CL5
+	 * bit18 - CL18
+	 */
+	pdimm->caslat_X  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
+
+	/*
+	 * min CAS latency time
+	 * eg: tAA_min =
+	 * DDR3-800D	100 MTB (12.5ns)
+	 * DDR3-1066F	105 MTB (13.125ns)
+	 * DDR3-1333H	108 MTB (13.5ns)
+	 * DDR3-1600H	90 MTB (11.25ns)
+	 */
+	pdimm->tAA_ps = spd->tAA_min * mtb_ps;
+
+	/*
+	 * min write recovery time
+	 * eg:
+	 * tWR_min = 120 MTB (15ns) -> all speed grades.
+	 */
+	pdimm->tWR_ps = spd->tWR_min * mtb_ps;
+
+	/*
+	 * min RAS to CAS delay time
+	 * eg: tRCD_min =
+	 * DDR3-800	100 MTB (12.5ns)
+	 * DDR3-1066F	105 MTB (13.125ns)
+	 * DDR3-1333H	108 MTB (13.5ns)
+	 * DDR3-1600H	90 MTB (11.25)
+	 */
+	pdimm->tRCD_ps = spd->tRCD_min * mtb_ps;
+
+	/*
+	 * min row active to row active delay time
+	 * eg: tRRD_min =
+	 * DDR3-800(1KB page)	80 MTB (10ns)
+	 * DDR3-1333(1KB page)	48 MTB (6ns)
+	 */
+	pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
+
+	/*
+	 * min row precharge delay time
+	 * eg: tRP_min =
+	 * DDR3-800D	100 MTB (12.5ns)
+	 * DDR3-1066F	105 MTB (13.125ns)
+	 * DDR3-1333H	108 MTB (13.5ns)
+	 * DDR3-1600H	90 MTB (11.25ns)
+	 */
+	pdimm->tRP_ps = spd->tRP_min * mtb_ps;
+
+	/* min active to precharge delay time
+	 * eg: tRAS_min =
+	 * DDR3-800D	300 MTB (37.5ns)
+	 * DDR3-1066F	300 MTB (37.5ns)
+	 * DDR3-1333H	288 MTB (36ns)
+	 * DDR3-1600H	280 MTB (35ns)
+	 */
+	pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
+			* mtb_ps;
+	/*
+	 * min active to actice/refresh delay time
+	 * eg: tRC_min =
+	 * DDR3-800D	400 MTB (50ns)
+	 * DDR3-1066F	405 MTB (50.625ns)
+	 * DDR3-1333H	396 MTB (49.5ns)
+	 * DDR3-1600H	370 MTB (46.25ns)
+	 */
+	pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
+			* mtb_ps;
+	/*
+	 * min refresh recovery delay time
+	 * eg: tRFC_min =
+	 * 512Mb	720 MTB (90ns)
+	 * 1Gb		880 MTB (110ns)
+	 * 2Gb		1280 MTB (160ns)
+	 */
+	pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
+			* mtb_ps;
+	/*
+	 * min internal write to read command delay time
+	 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
+	 * tWRT is at least 4 mclk independent of operating freq.
+	 */
+	pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
+
+	/*
+	 * min internal read to precharge command delay time
+	 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
+	 * tRTP is at least 4 mclk independent of operating freq.
+	 */
+	pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
+
+	/*
+	 * Average periodic refresh interval
+	 * tREFI = 7.8 us at normal temperature range
+	 *       = 3.9 us at ext temperature range
+	 */
+	pdimm->refresh_rate_ps = 7800000;
+
+	/*
+	 * min four active window delay time
+	 * eg: tFAW_min =
+	 * DDR3-800(1KB page)	320 MTB (40ns)
+	 * DDR3-1066(1KB page)	300 MTB (37.5ns)
+	 * DDR3-1333(1KB page)	240 MTB (30ns)
+	 * DDR3-1600(1KB page)	240 MTB (30ns)
+	 */
+	pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
+			* mtb_ps;
+
+	/*
+	 * We need check the address mirror for unbuffered DIMM
+	 * If SPD indicate the address map mirror, The DDR controller
+	 * need care it.
+	 */
+	if ((spd->module_type == SPD_MODULETYPE_UDIMM) ||
+	    (spd->module_type == SPD_MODULETYPE_SODIMM) ||
+	    (spd->module_type == SPD_MODULETYPE_MICRODIMM) ||
+	    (spd->module_type == SPD_MODULETYPE_MINIUDIMM))
+		pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1;
+
+	return 0;
+}

cpu/mpc8xxx/ddr/lc_common_dimm_params.c

@@ -11,6 +11,59 @@
 
 #include "ddr.h"
 
+unsigned int
+compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
+			 common_timing_params_t *outpdimm,
+			 unsigned int number_of_dimms)
+{
+	unsigned int i;
+	unsigned int tAAmin_ps = 0;
+	unsigned int tCKmin_X_ps = 0;
+	unsigned int common_caslat;
+	unsigned int caslat_actual;
+	unsigned int retry = 16;
+	unsigned int tmp;
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+
+	/* compute the common CAS latency supported between slots */
+	tmp = dimm_params[0].caslat_X;
+	for (i = 1; i < number_of_dimms; i++)
+		 tmp &= dimm_params[i].caslat_X;
+	common_caslat = tmp;
+
+	/* compute the max tAAmin tCKmin between slots */
+	for (i = 0; i < number_of_dimms; i++) {
+		tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
+		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
+	}
+	/* validate if the memory clk is in the range of dimms */
+	if (mclk_ps < tCKmin_X_ps) {
+		printf("The DIMM max tCKmin is %d ps,"
+			"doesn't support the MCLK cycle %d ps\n",
+			tCKmin_X_ps, mclk_ps);
+		return 1;
+	}
+	/* determine the acutal cas latency */
+	caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
+	/* check if the dimms support the CAS latency */
+	while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
+		caslat_actual++;
+		retry--;
+	}
+	/* once the caculation of caslat_actual is completed
+	 * we must verify that this CAS latency value does not
+	 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
+	 */
+	if (caslat_actual * mclk_ps > 20000) {
+		printf("The choosen cas latency %d is too large\n",
+			caslat_actual);
+		return 1;
+	}
+	outpdimm->lowest_common_SPD_caslat = caslat_actual;
+
+	return 0;
+}
+
 /*
  * compute_lowest_common_dimm_parameters()
  *
@@ -46,12 +99,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	unsigned int tQHS_ps = 0;
 
 	unsigned int temp1, temp2;
-	unsigned int lowest_good_caslat;
 	unsigned int additive_latency = 0;
+#if !defined(CONFIG_FSL_DDR3)
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	unsigned int lowest_good_caslat;
 	unsigned int not_ok;
 
 	debug("using mclk_ps = %u\n", mclk_ps);
+#endif
 
 	temp1 = 0;
 	for (i = 0; i < number_of_dimms; i++) {
@@ -164,6 +219,10 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				"DIMMs detected!\n");
 	}
 
+#if defined(CONFIG_FSL_DDR3)
+	if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
+		return 1;
+#else
 	/*
 	 * Compute a CAS latency suitable for all DIMMs
 	 *
@@ -281,6 +340,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	}
 	outpdimm->highest_common_derated_caslat = temp1;
 	debug("highest common dereated CAS latency = %u\n", temp1);
+#endif /* #if defined(CONFIG_FSL_DDR3) */
 
 	/* Determine if all DIMMs ECC capable. */
 	temp1 = 1;
@@ -297,14 +357,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	}
 	outpdimm->all_DIMMs_ECC_capable = temp1;
 
-
+#ifndef CONFIG_FSL_DDR3
 	/* FIXME: move to somewhere else to validate. */
 	if (mclk_ps > tCKmax_max_ps) {
 		printf("Warning: some of the installed DIMMs "
 				"can not operate this slowly.\n");
 		return 1;
 	}
-
+#endif
 	/*
 	 * Compute additive latency.
 	 *
@@ -314,7 +374,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	 *	which comes from Trcd, and also note that:
 	 *	    add_lat + caslat must be >= 4
 	 *
-	 * For DDR3, FIXME additive latency determination
+	 * For DDR3, we use the AL=0
 	 *
 	 * When to use additive latency for DDR2:
 	 *
@@ -371,7 +431,11 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	}
 
 #elif defined(CONFIG_FSL_DDR3)
-error "FIXME determine additive latency for DDR3"
+	/*
+	 * The system will not use the global auto-precharge mode.
+	 * However, it uses the page mode, so we set AL=0
+	 */
+	additive_latency = 0;
 #endif
 
 	/*

cpu/mpc8xxx/ddr/options.c

@@ -96,10 +96,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 */
 #if defined(CONFIG_FSL_DDR1)
 	popts->DQS_config = 0;
-#elif defined(CONFIG_FSL_DDR2)
+#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 	popts->DQS_config = 1;
-#else
-#error "Fix DQS for DDR3"
 #endif
 
 	/* Choose self-refresh during sleep. */
@@ -112,7 +110,17 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	popts->data_bus_width = 0;
 
 	/* Choose burst length. */
-	popts->burst_length = 4;	/* has to be 4 for DDR2 */
+#if defined(CONFIG_FSL_DDR3)
+	popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
+	popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
+#else
+	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
+#endif
+
+	/* Choose ddr controller address mirror mode */
+#if defined(CONFIG_FSL_DDR3)
+	popts->mirrored_dimm = pdimm[0].mirrored_dimm;
+#endif
 
 	/* Global Timing Parameters. */
 	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
@@ -181,7 +189,17 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	popts->tFAW_window_four_activates_ps = 37500;
 
 #elif defined(CONFIG_FSL_DDR3)
-#error "FIXME determine four activates for DDR3"
+	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
+#endif
+	popts->zq_en = 0;
+	popts->wrlvl_en = 0;
+#if defined(CONFIG_FSL_DDR3)
+	/*
+	 * due to ddr3 dimm is fly-by topology
+	 * we suggest to enable write leveling to
+	 * meet the tQDSS under different loading.
+	 */
+	popts->wrlvl_en = 1;
 #endif
 
 	/*

drivers/misc/fsl_law.c

@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
     defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
 #define FSL_HW_NUM_LAWS 8
 #elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
-      defined(CONFIG_MPC8568) || \
+      defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) || \
       defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
 #define FSL_HW_NUM_LAWS 10
 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \

drivers/qe/qe.c

@@ -161,6 +161,15 @@ void qe_init(uint qe_base)
 	/* Init the QE IMMR base */
 	qe_immr = (qe_map_t *)qe_base;
 
+#ifdef CONFIG_SYS_QE_FW_ADDR
+        /* Upload microcode to IRAM for those SOCs which do not have ROM in QE.
+         */
+        qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR);
+
+        /* enable the microcode in IRAM */
+        out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
+#endif
+
 	gd->mp_alloc_base = QE_DATAONLY_BASE;
 	gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
 

drivers/qe/qe.h

@@ -230,6 +230,7 @@ typedef enum qe_clock {
 /* I-RAM */
 #define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
 #define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
+#define QE_IRAM_READY		0x80000000
 
 /* Structure that defines QE firmware binary files.
  *

include/asm-ppc/fsl_ddr_dimm_params.h

@@ -33,9 +33,15 @@ typedef struct dimm_params_s {
 
 	/* used in computing base address of DIMMs */
 	unsigned long long base_address;
+	/* mirrored DIMMs */
+	unsigned int mirrored_dimm;	/* only for ddr3 */
 
 	/* DIMM timing parameters */
 
+	unsigned int mtb_ps;	/* medium timebase ps, only for ddr3 */
+	unsigned int tAA_ps;	/* minimum CAS latency time, only for ddr3 */
+	unsigned int tFAW_ps;	/* four active window delay, only for ddr3 */
+
 	/*
 	 * SDRAM clock periods
 	 * The range for these are 1000-10000 so a short should be sufficient
@@ -67,6 +73,7 @@ typedef struct dimm_params_s {
 
 	unsigned int refresh_rate_ps;
 
+	/* DDR3 doesn't need these as below */
 	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
 	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
 	unsigned int tDS_ps;	/* byte 34, spd->data_setup */

include/asm-ppc/fsl_ddr_sdram.h

@@ -19,6 +19,11 @@
 #define SDRAM_TYPE_LPDDR1  6
 #define SDRAM_TYPE_DDR3    7
 
+#define DDR_BL4		4	/* burst length 4 */
+#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
+#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
+#define DDR_BL8		8	/* burst length 8 */
+
 #if defined(CONFIG_FSL_DDR1)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
@@ -68,6 +73,18 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN			0x00008000
 #define SDRAM_CFG_BI			0x00000001
 
+#if defined(CONFIG_P4080)
+#define RD_TO_PRE_MASK		0xf
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0xf
+#define WR_DATA_DELAY_SHIFT	9
+#else
+#define RD_TO_PRE_MASK		0x7
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0x7
+#define WR_DATA_DELAY_SHIFT	10
+#endif
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
 	struct {
@@ -145,7 +162,11 @@ typedef struct memctl_options_s {
 	unsigned int dynamic_power;	/* DYN_PWR */
 	/* memory data width to use (16-bit, 32-bit, 64-bit) */
 	unsigned int data_bus_width;
-	unsigned int burst_length;	/* 4, 8 */
+	unsigned int burst_length;	/* BL4, OTF and BL8 */
+	/* On-The-Fly Burst Chop enable */
+	unsigned int OTF_burst_chop_en;
+	/* mirrior DIMMs for DDR3 */
+	unsigned int mirrored_dimm;
 
 	/* Global Timing Parameters */
 	unsigned int cas_latency_override;
@@ -164,9 +185,17 @@ typedef struct memctl_options_s {
 	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
 	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
 
+	/* Rtt impedance */
+	unsigned int rtt_override;		/* rtt_override enable */
+	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
+
 	/* Automatic self refresh */
 	unsigned int auto_self_refresh_en;
 	unsigned int sr_it;
+	/* ZQ calibration */
+	unsigned int zq_en;
+	/* Write leveling */
+	unsigned int wrlvl_en;
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);

include/asm-ppc/fsl_lbc.h

@@ -397,6 +397,33 @@
 #define FPAR_LP_CI             0x000007FF
 #define FPAR_LP_CI_SHIFT       0
 
+/* LSDMR - SDRAM Machine Mode Register
+ */
+#define LSDMR_RFEN	(1 << (31 -  1))
+#define LSDMR_BSMA1516	(3 << (31 - 10))
+#define LSDMR_BSMA1617	(4 << (31 - 10))
+#define LSDMR_RFCR5	(3 << (31 - 16))
+#define LSDMR_RFCR16	(7 << (31 - 16))
+#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT7	(7 << (31 - 19))
+#define LSDMR_ACTTORW3	(3 << (31 - 22))
+#define LSDMR_ACTTORW7	(7 << (31 - 22))
+#define LSDMR_ACTTORW6	(6 << (31 - 22))
+#define LSDMR_BL8	(1 << (31 - 23))
+#define LSDMR_WRC2	(2 << (31 - 27))
+#define LSDMR_WRC4	(0 << (31 - 27))
+#define LSDMR_BUFCMD	(1 << (31 - 29))
+#define LSDMR_CL3	(3 << (31 - 31))
+
+#define LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define LSDMR_OP_MRW	(3 << (31 - 4))
+#define LSDMR_OP_PRECH	(4 << (31 - 4))
+#define LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define LSDMR_OP_RWINV	(7 << (31 - 4))
+
 /* LTESR - Transfer Error Status Register
  */
 #define LTESR_BM               0x80000000

include/asm-ppc/immap_85xx.h

@@ -1609,8 +1609,19 @@ typedef struct ccsr_gur {
 	char	res2[12];
 	uint	gpiocr;		/* 0xe0030 - GPIO control register */
 	char	res3[12];
+#if defined(CONFIG_MPC8569)
+	uint	plppar1;
+			/* 0xe0040 - Platform port pin assignment register 1 */
+	uint	plppar2;
+			/* 0xe0044 - Platform port pin assignment register 2 */
+	uint	plpdir1;
+			/* 0xe0048 - Platform port pin direction register 1 */
+	uint	plpdir2;
+			/* 0xe004c - Platform port pin direction register 2 */
+#else
 	uint	gpoutdr;	/* 0xe0040 - General-purpose output data register */
 	char	res4[12];
+#endif
 	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
 	char	res5[12];
 	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
@@ -1651,7 +1662,7 @@ typedef struct ccsr_gur {
 	uint	svr;		/* 0xe00a4 - System version register */
 	char	res10a[8];
 	uint	rstcr;		/* 0xe00b0 - Reset control register */
-#ifdef CONFIG_MPC8568
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
 	char	res10b[76];
 	par_io_t qe_par_io[7];  /* 0xe0100 - 0xe01bf */
 	char	res10c[3136];

include/asm-ppc/immap_qe.h

@@ -20,7 +20,9 @@
 typedef struct qe_iram {
 	u32 iadd;		/* I-RAM Address Register */
 	u32 idata;		/* I-RAM Data Register    */
-	u8 res0[0x78];
+	u8 res0[0x4];
+	u32 iready;
+	u8 res1[0x70];
 } __attribute__ ((packed)) qe_iram_t;
 
 /* QE Interrupt Controller
@@ -580,7 +582,7 @@ typedef struct qe_immap {
 	u8 res14[0x300];
 	u8 res15[0x3A00];
 	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
-#if defined(CONFIG_MPC8568)
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
 	u8 muram[0x10000];	/* 0x1_0000 -  0x2_0000 Multi-user RAM */
 	u8 res17[0x20000];	/* 0x2_0000 -  0x4_0000 */
 #else
@@ -592,7 +594,7 @@ typedef struct qe_immap {
 
 extern qe_map_t *qe_immr;
 
-#if defined(CONFIG_MPC8568)
+#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
 #define QE_MURAM_SIZE		0x10000UL
 #elif defined(CONFIG_MPC8360)
 #define QE_MURAM_SIZE		0xc000UL

include/asm-ppc/mp.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_MP_H_
+#define _ASM_MP_H_
+
+#include <lmb.h>
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+u32 determine_mp_bootpg(void);
+
+#endif
+

include/asm-ppc/processor.h

@@ -955,6 +955,8 @@
 #define SVR_8567_E	0x807E00
 #define SVR_8568	0x807500
 #define SVR_8568_E	0x807D00
+#define SVR_8569	0x808000
+#define SVR_8569_E	0x808800
 #define SVR_8572	0x80E000
 #define SVR_8572_E	0x80E800
 #define SVR_P2020	0x80E200

include/configs/MPC8323ERDB.h

@@ -248,34 +248,8 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
-
 #endif
 
 /*

include/configs/MPC832XEMDS.h

@@ -246,34 +246,8 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
-
 #endif
 
 /*

include/configs/MPC8349EMDS.h

@@ -262,60 +262,24 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
-				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC3		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
+				| LSDMR_BSMA1516	\
+				| LSDMR_RFCR8		\
+				| LSDMR_PRETOACT6	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC3		\
+				| LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 #endif
 
 /*

include/configs/MPC8360EMDS.h

@@ -271,33 +271,16 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
 #endif
 

include/configs/MPC8540ADS.h

@@ -197,57 +197,24 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR5		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT3	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC2		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
 
 /*

include/configs/MPC8541CDS.h

@@ -206,42 +206,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*

include/configs/MPC8548CDS.h

@@ -228,42 +228,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *		    or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*

include/configs/MPC8555CDS.h

@@ -204,42 +204,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*

include/configs/MPC8560ADS.h

@@ -193,57 +193,24 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR5		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT3	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC2		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
 
 /*

include/configs/MPC8568MDS.h

@@ -187,42 +187,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*

include/configs/MPC8569MDS.h

@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8569mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
+#define CONFIG_MPC8569		1	/* MPC8569 specific */
+#define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
+
+#define CONFIG_PCI		1	/* Disable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_QE			/* Enable QE */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the MDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define CONFIG_DDR_CLK_FREQ	66000000
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
+						/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
+						/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+					/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2    0x52    /* CTLR 1 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
+#define CONFIG_SYS_DDR_TIMING_3         0x00020000
+#define CONFIG_SYS_DDR_TIMING_0         0x00330004
+#define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
+#define CONFIG_SYS_DDR_TIMING_2         0x002888D0
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
+#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
+#define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
+#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
+#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
+#define CONFIG_SYS_DDR_TIMING_4         0x00220001
+#define CONFIG_SYS_DDR_TIMING_5         0x03402400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
+#define CONFIG_SYS_DDR_CDR_1		0x80040000
+#define CONFIG_SYS_DDR_CDR_2		0x00000000
+#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
+#define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL2         0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
+#define CONFIG_SYS_DDR_SBE              0x00010000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
+
+/*Chip select 0 - Flash*/
+#define CONFIG_SYS_BR0_PRELIM		0xfe000801
+#define	CONFIG_SYS_OR0_PRELIM		0xfe000ff7
+
+/*Chip slelect 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the LocalBus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM       1
+
+#define PLPPAR1_I2C_BIT_MASK		0x0000000F
+#define PLPPAR1_I2C2_VAL		0x00000000
+#define PLPDIR1_I2C_BIT_MASK		0x0000000F
+#define PLPDIR1_I2C2_VAL		0x0000000F
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
+#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
+
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME         "FSL UEC0"
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#endif /* CONFIG_QE */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_ADDR	0xfff00000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
+					/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME mpc8569mds
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=600000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=your.fdt.dtb\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"run nfsargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"run ramargs;"							\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */

include/configs/MPC8641HPCN.h

@@ -36,6 +36,7 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
+#define CONFIG_MP		1	/* support multiple processors */
 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */

include/configs/sbc8349.h

@@ -227,60 +227,24 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
-				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC3		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
+				| LSDMR_BSMA1516	\
+				| LSDMR_RFCR8		\
+				| LSDMR_PRETOACT6	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC3		\
+				| LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 #endif
 
 /*

include/configs/sbc8548.h

@@ -241,42 +241,19 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1

include/configs/sbc8641d.h

@@ -40,6 +40,7 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_SBC8641D		1	/* SBC8641D board specific */
+#define CONFIG_MP		1	/* support multiple processors */
 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
 

include/ddr_spd.h

@@ -184,7 +184,7 @@ typedef struct ddr3_spd_eeprom_s {
 	unsigned char module_type;     /*  3 Key Byte / Module Type */
 	unsigned char density_banks;   /*  4 SDRAM Density and Banks */
 	unsigned char addressing;      /*  5 SDRAM Addressing */
-	unsigned char res_6;           /*  6 Reserved */
+	unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
 	unsigned char organization;    /*  7 Module Organization */
 	unsigned char bus_width;       /*  8 Module Memory Bus Width */
 	unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
@@ -273,6 +273,7 @@ extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
 extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
 extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
 extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
+extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
 
 /*
  * Byte 2 Fundamental Memory Types.
@@ -289,4 +290,14 @@ extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE	(0x0A)
 #define SPD_MEMTYPE_DDR3	(0x0B)
 
+/*
+ * Byte 3 Key Byte / Module Type for DDR3 SPD
+ */
+#define SPD_MODULETYPE_RDIMM		(0x01)
+#define SPD_MODULETYPE_UDIMM		(0x02)
+#define SPD_MODULETYPE_SODIMM		(0x03)
+#define SPD_MODULETYPE_MICRODIMM	(0x04)
+#define SPD_MODULETYPE_MINIRDIMM	(0x05)
+#define SPD_MODULETYPE_MINIUDIMM	(0x06)
+
 #endif /* _DDR_SPD_H_ */

lib_ppc/board.c

@@ -79,6 +79,10 @@
 #include <asm/mmu.h>
 #endif
 
+#ifdef CONFIG_MP
+#include <asm/mp.h>
+#endif
+
 #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
 extern int update_flash_size (int flash_size);
 #endif
@@ -444,6 +448,17 @@ void board_init_f (ulong bootflag)
 
 	addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
 
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+	/*
+	 * We need to make sure the location we intend to put secondary core
+	 * boot code is reserved and not used by any part of u-boot
+	 */ 
+	if (addr > determine_mp_bootpg()) {
+		addr = determine_mp_bootpg();
+		debug ("Reserving MP boot page to %08lx\n", addr);
+	}
+#endif
+
 #ifdef CONFIG_LOGBUFFER
 #ifndef CONFIG_ALT_LB_ADDR
 	/* reserve kernel log buffer */