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@@ -38,7 +38,7 @@
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#define CONFIG_MCFUART
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#define CONFIG_SYS_UART_PORT (0)
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-#define CONFIG_BAUDRATE 9600
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+#define CONFIG_BAUDRATE 115200
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#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
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#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
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@@ -52,20 +52,24 @@
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN
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+#define CONFIG_HW_WATCHDOG
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+
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+#define CONFIG_STATUS_LED
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+#define CONFIG_BOARD_SPECIFIC_LED
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+#define STATUS_LED_ACTIVE 0
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+#define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */
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+#define STATUS_LED_BOOT 0
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+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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+#define STATUS_LED_STATE STATUS_LED_OFF
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+
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/*----------------------------------------------------------------------*
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/*----------------------------------------------------------------------*
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* Configuration for environment *
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* Configuration for environment *
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* Environment is in the second sector of the first 256k of flash *
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* Environment is in the second sector of the first 256k of flash *
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*----------------------------------------------------------------------*/
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*----------------------------------------------------------------------*/
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-#ifndef CONFIG_MONITOR_IS_IN_RAM
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-#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
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-#define CONFIG_ENV_SECT_SIZE 0x4000
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-#define CONFIG_ENV_IS_IN_FLASH 1
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-#else
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-#define CONFIG_ENV_ADDR 0xFFE04000
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-#define CONFIG_ENV_SECT_SIZE 0x2000
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+#define CONFIG_ENV_ADDR 0xFF040000
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+#define CONFIG_ENV_SECT_SIZE 0x00020000
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_IS_IN_FLASH 1
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-#endif
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/*
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/*
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* BOOTP options
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* BOOTP options
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@@ -78,26 +82,24 @@
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/*
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/*
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* Command line configuration.
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* Command line configuration.
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*/
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*/
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+#define CONFIG_CMDLINE_EDITING
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#include <config_cmd_default.h>
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_LOADB
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+#define CONFIG_CMD_DATE
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+#define CONFIG_CMD_DHCP
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+#define CONFIG_CMD_I2C
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+#define CONFIG_CMD_LED
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NET
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#define CONFIG_MCFTMR
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#define CONFIG_MCFTMR
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-
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOTDELAY 5
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-#define CONFIG_SYS_HUSH_PARSER
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-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
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#define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_SYS_LONGHELP 1
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-#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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-#else
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-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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-#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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@@ -112,12 +114,12 @@
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/*----------------------------------------------------------------------*
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/*----------------------------------------------------------------------*
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* Clock and PLL Configuration *
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* Clock and PLL Configuration *
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*----------------------------------------------------------------------*/
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*----------------------------------------------------------------------*/
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-#define CONFIG_SYS_HZ 10000000
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-#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
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+#define CONFIG_SYS_HZ 1000
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+#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
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-/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
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+/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
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-#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
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+#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
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#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
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#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
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/*----------------------------------------------------------------------*
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/*----------------------------------------------------------------------*
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@@ -135,7 +137,6 @@
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#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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#define MCFFEC_TOUT_LOOP 50000
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#define MCFFEC_TOUT_LOOP 50000
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-#define CONFIG_ETHADDR 00:CF:52:82:EB:01
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*-------------------------------------------------------------------------
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/*-------------------------------------------------------------------------
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@@ -151,7 +152,7 @@
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*-----------------------------------------------------------------------*/
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*-----------------------------------------------------------------------*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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@@ -161,12 +162,11 @@
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* (Set up by the startup code)
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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*/
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-#define CONFIG_SYS_SDRAM_BASE1 0x00000000
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-#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
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-
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-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
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-#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
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+#define CONFIG_SYS_SDRAM_BASE0 0x00000000
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+#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
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+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
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+#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
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/* If M5282 port is fully implemented the monitor base will be behind
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/* If M5282 port is fully implemented the monitor base will be behind
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* the vector table. */
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* the vector table. */
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@@ -190,16 +190,24 @@
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* FLASH organization
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* FLASH organization
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*/
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*/
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+#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
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#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
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#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
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#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
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-#define CONFIG_SYS_MAX_FLASH_SECT 35
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-#define CONFIG_SYS_MAX_FLASH_BANKS 2
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+#define CONFIG_SYS_MAX_FLASH_SECT 128
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+#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
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#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_PROTECTION
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+#define CONFIG_SYS_FLASH_CFI
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+#define CONFIG_FLASH_CFI_DRIVER
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+#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
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+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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+
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+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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+
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* Cache Configuration
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* Cache Configuration
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*/
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*/
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@@ -221,12 +229,16 @@
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* Memory bank definitions
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* Memory bank definitions
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*/
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*/
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-#define CONFIG_SYS_CS0_BASE 0xFFE00000
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+#define CONFIG_SYS_CS0_BASE 0xFF000000
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#define CONFIG_SYS_CS0_CTRL 0x00001980
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#define CONFIG_SYS_CS0_CTRL 0x00001980
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-#define CONFIG_SYS_CS0_MASK 0x001F0001
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+#define CONFIG_SYS_CS0_MASK 0x00FF0001
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-#define CONFIG_SYS_CS3_BASE 0xE0000000
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-#define CONFIG_SYS_CS0_CTRL 0x00001980
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+#define CONFIG_SYS_CS2_BASE 0xE0000000
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+#define CONFIG_SYS_CS2_CTRL 0x00001980
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+#define CONFIG_SYS_CS2_MASK 0x000F0001
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+
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+#define CONFIG_SYS_CS3_BASE 0xE0100000
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+#define CONFIG_SYS_CS3_CTRL 0x00001980
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#define CONFIG_SYS_CS3_MASK 0x000F0001
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#define CONFIG_SYS_CS3_MASK 0x000F0001
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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@@ -248,11 +260,30 @@
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#define CONFIG_SYS_PCDDR 0x0000000
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#define CONFIG_SYS_PCDDR 0x0000000
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#define CONFIG_SYS_PCDAT 0x0000000
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#define CONFIG_SYS_PCDAT 0x0000000
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+#define CONFIG_SYS_PASPAR 0x0F0F
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#define CONFIG_SYS_PEHLPAR 0xC0
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#define CONFIG_SYS_PEHLPAR 0xC0
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#define CONFIG_SYS_PUAPAR 0x0F
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#define CONFIG_SYS_PUAPAR 0x0F
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#define CONFIG_SYS_DDRUA 0x05
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#define CONFIG_SYS_DDRUA 0x05
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#define CONFIG_SYS_PJPAR 0xFF
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#define CONFIG_SYS_PJPAR 0xFF
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+/*-----------------------------------------------------------------------
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+ * I2C
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+ */
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+
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+#define CONFIG_HARD_I2C
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+#define CONFIG_FSL_I2C
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+
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+#define CONFIG_SYS_I2C_OFFSET 0x00000300
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+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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+
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+#define CONFIG_SYS_I2C_SPEED 100000
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+#define CONFIG_SYS_I2C_SLAVE 0
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+
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+#ifdef CONFIG_CMD_DATE
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+#define CONFIG_RTC_DS1338
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+#define CONFIG_I2C_RTC_ADDR 0x68
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+#endif
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+
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* VIDEO configuration
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* VIDEO configuration
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*/
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*/
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@@ -260,12 +291,11 @@
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO
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#ifdef CONFIG_VIDEO
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#ifdef CONFIG_VIDEO
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-#define CONFIG_VIDEO_VCXK 1
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+#define CONFIG_VIDEO_VCXK 1
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#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
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#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
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#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
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#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
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-#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE
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-#define CONFIG_SYS_VCXK_AUTODETECT 1
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+#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
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