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@@ -161,12 +161,12 @@
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#define MIIM_DM9161_10BTCSR_INIT 0x7800
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#define MIIM_DM9161_10BTCSR_INIT 0x7800
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/* LXT971 Status 2 registers */
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/* LXT971 Status 2 registers */
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-#define MIIM_LXT971_SR2 17 /* Status Register 2 */
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-#define MIIM_LXT971_SR2_SPEED_MASK 0xf000
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-#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */
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-#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */
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-#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
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-#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */
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+#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
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+#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
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+#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
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+#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
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+#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
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+#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
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#define MIIM_READ_COMMAND 0x00000001
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#define MIIM_READ_COMMAND 0x00000001
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