Merge branch 'next' of git://git.denx.de/u-boot-video into next

board/lwmon5/lwmon5.c

@@ -532,13 +532,6 @@ unsigned int board_video_init (void)
 	udelay(500);
 	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
 
-	/* Lime memory clock adjusted to 100MHz */
-	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
-	/* Wait untill time expired. Because of requirements in lime manual */
-	udelay(300);
-	/* Write lime controller memory parameters */
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
-
 	mb862xx.winSizeX = 640;
 	mb862xx.winSizeY = 480;
 	mb862xx.gdfBytesPP = 2;

board/socrates/socrates.c

@@ -268,17 +268,6 @@ ft_board_setup(void *blob, bd_t *bd)
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 
-#define CONFIG_SYS_LIME_SRST		((CONFIG_SYS_LIME_BASE) + 0x01FC002C)
-#define CONFIG_SYS_LIME_CCF		((CONFIG_SYS_LIME_BASE) + 0x01FC0038)
-#define CONFIG_SYS_LIME_MMR		((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC)
-/* Lime clock frequency */
-#define CONFIG_SYS_LIME_CLK_100MHZ	0x00000
-#define CONFIG_SYS_LIME_CLK_133MHZ	0x10000
-/* SDRAM parameter */
-#define CONFIG_SYS_LIME_MMR_VALUE	0x4157BA63
-
-#define DISPLAY_WIDTH		800
-#define DISPLAY_HEIGHT		480
 #define DEFAULT_BRIGHTNESS	25
 #define BACKLIGHT_ENABLE	(1 << 31)
 
@@ -308,14 +297,12 @@ const gdc_regs *board_get_regs (void)
 	return init_regs;
 }
 
-#define CONFIG_SYS_LIME_CID		((CONFIG_SYS_LIME_BASE) + 0x01FC00F0)
-#define CONFIG_SYS_LIME_REV		((CONFIG_SYS_LIME_BASE) + 0x01FF8084)
 int lime_probe(void)
 {
 	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint cfg_br2;
 	uint cfg_or2;
-	uint reg;
+	int type;
 
 	cfg_br2 = memctl->br2;
 	cfg_or2 = memctl->or2;
@@ -325,21 +312,15 @@ int lime_probe(void)
 	memctl->or2 = 0xfc000410;
 	memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
 
-	/* Try to access GDC ID/Revision registers */
-	reg = in_be32((void *)CONFIG_SYS_LIME_CID);
-	reg = in_be32((void *)CONFIG_SYS_LIME_CID);
-	if (reg == 0x303) {
-		reg = in_be32((void *)CONFIG_SYS_LIME_REV);
-		reg = in_be32((void *)CONFIG_SYS_LIME_REV);
-		reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
-	} else
-		reg = 0;
+	/* Get controller type */
+	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
 
 	/* Restore previous CS2 configuration */
 	memctl->br2 = 0;
 	memctl->or2 = cfg_or2;
 	memctl->br2 = cfg_br2;
-	return reg;
+
+	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
 }
 
 /* Returns Lime base address */
@@ -348,21 +329,8 @@ unsigned int board_video_init (void)
 	if (!lime_probe())
 		return 0;
 
-	/*
-	 * Reset Lime controller
-	 */
-	out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1);
-	udelay(200);
-
-	/* Set Lime clock to 133MHz */
-	out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ);
-	/* Delay required */
-	udelay(300);
-	/* Set memory parameters */
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
-
-	mb862xx.winSizeX = DISPLAY_WIDTH;
-	mb862xx.winSizeY = DISPLAY_HEIGHT;
+	mb862xx.winSizeX = 800;
+	mb862xx.winSizeY = 480;
 	mb862xx.gdfIndex = GDF_15BIT_555RGB;
 	mb862xx.gdfBytesPP = 2;
 

drivers/video/cfb_console.c

@@ -146,9 +146,11 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
 #ifdef CONFIG_VIDEO_CORALP
 #define VIDEO_FB_LITTLE_ENDIAN
 #endif
+#ifdef CONFIG_VIDEO_MB862xx_ACCEL
 #define VIDEO_HW_RECTFILL
 #define VIDEO_HW_BITBLT
 #endif
+#endif
 
 /*****************************************************************************/
 /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc	     */
@@ -319,7 +321,7 @@ void	console_cursor (int state);
 #else
 #define SWAP16(x)	 (x)
 #define SWAP32(x)	 (x)
-#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
+#if defined(VIDEO_FB_16BPP_WORD_SWAP)
 #define SHORTSWAP32(x)	 ( ((x) >> 16) | ((x) << 16) )
 #else
 #define SHORTSWAP32(x)	 (x)

drivers/video/mb862xx.c

@@ -89,6 +89,7 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
 				       (GC_DISP_BASE | GC_L0PAL0) + \
 				       ((idx) << 2)), (val))
 
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
 static void gdc_sw_reset (void)
 {
 	GraphicDevice *dev = &mb862xx;
@@ -129,6 +130,7 @@ static void de_wait_slots (int slots)
 			break;
 		}
 }
+#endif
 
 #if !defined(CONFIG_VIDEO_CORALP)
 static void board_disp_init (void)
@@ -144,11 +146,13 @@ static void board_disp_init (void)
 #endif
 
 /*
- * Init drawing engine
+ * Init drawing engine if accel enabled.
+ * Also clears visible framebuffer.
  */
 static void de_init (void)
 {
 	GraphicDevice *dev = &mb862xx;
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
 	int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
 
 	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
@@ -174,6 +178,14 @@ static void de_init (void)
 	DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
 	/* sync with SW access to framebuffer */
 	de_wait ();
+#else
+	unsigned int i, *p;
+
+	i = dev->winSizeX * dev->winSizeY;
+	p = (unsigned int *)dev->frameAdrs;
+	while (i--)
+		*p++ = 0;
+#endif
 }
 
 #if defined(CONFIG_VIDEO_CORALP)
@@ -340,6 +352,30 @@ unsigned int card_init (void)
 }
 #endif
 
+
+#if !defined(CONFIG_VIDEO_CORALP)
+int mb862xx_probe(unsigned int addr)
+{
+	GraphicDevice *dev = &mb862xx;
+	unsigned int reg;
+
+	dev->frameAdrs = addr;
+	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
+
+	/* Try to access GDC ID/Revision registers */
+	reg = HOST_RD_REG (GC_CID);
+	reg = HOST_RD_REG (GC_CID);
+	if (reg == 0x303) {
+		reg = DE_RD_REG(GC_REV);
+		reg = DE_RD_REG(GC_REV);
+		if ((reg & ~0xff) == 0x20050100)
+			return MB862XX_TYPE_LIME;
+	}
+
+	return 0;
+}
+#endif
+
 void *video_hw_init (void)
 {
 	GraphicDevice *dev = &mb862xx;
@@ -359,8 +395,16 @@ void *video_hw_init (void)
 	if ((dev->frameAdrs = board_video_init ()) == 0) {
 		puts ("Controller not found!\n");
 		return NULL;
-	} else
+	} else {
 		puts ("Lime\n");
+
+		/* Set Change of Clock Frequency Register */
+		HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
+		/* Delay required */
+		udelay(300);
+		/* Set Memory I/F Mode Register) */
+		HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
+	}
 #endif
 
 	de_init ();
@@ -389,6 +433,7 @@ void video_set_lut (unsigned int index, unsigned char r,
 	L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
 }
 
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
 /*
  * Drawing engine Fill and BitBlt screen region
  */
@@ -430,3 +475,4 @@ void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
 	DE_WR_FIFO ((height << 16) | width);
 	de_wait (); /* sync */
 }
+#endif

include/configs/lwmon5.h

@@ -344,10 +344,12 @@
 /* Video console */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
 
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_SW_CURSOR
@@ -495,8 +497,6 @@
 /*-----------------------------------------------------------------------
  * Graphics (Fujitsu Lime)
  *----------------------------------------------------------------------*/
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK	0xC1FC0038
 /* Lime Clock frequency is to set 100MHz */
 #define CONFIG_SYS_LIME_CLOCK_100MHZ	0x00000
 #if 0
@@ -504,15 +504,15 @@
 #define CONFIG_SYS_LIME_CLOCK_133MHZ	0x10000
 #endif
 
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR		0xC1FCFFFC
 /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
    and pixel flare on display when 133MHz was configured. According to
    SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_LIME_MMR_VALUE	0x414FB7F3
+#define CONFIG_SYS_MB862xx_MMR	0x414FB7F3
+#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_133MHZ
 #else
-#define CONFIG_SYS_LIME_MMR_VALUE	0x414FB7F2
+#define CONFIG_SYS_MB862xx_MMR	0x414FB7F2
+#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_100MHZ
 #endif
 
 /*-----------------------------------------------------------------------

include/configs/socrates.h

@@ -198,11 +198,13 @@
 
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_VIDEO_SW_CURSOR
@@ -210,6 +212,11 @@
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
 
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF		0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR		0x4157BA63
+
 /* Serial Port */
 
 #define CONFIG_CONS_INDEX     1

include/mb862xx.h

@@ -32,6 +32,8 @@
 #define PCI_DEVICE_ID_CORAL_P	0x2019
 #define PCI_DEVICE_ID_CORAL_PA	0x201E
 
+#define MB862XX_TYPE_LIME	0x1
+
 #define GC_HOST_BASE		0x01fc0000
 #define GC_DISP_BASE		0x01fd0000
 #define GC_DRAW_BASE		0x01ff0000
@@ -39,6 +41,7 @@
 /* Host interface registers */
 #define GC_SRST			0x0000002c
 #define GC_CCF			0x00000038
+#define GC_CID			0x000000f0
 #define GC_MMR			0x0000fffc
 
 /*
@@ -99,6 +102,7 @@
 #define GC_FC			0x00000480
 #define GC_BC			0x00000484
 #define GC_FIFO			0x000004a0
+#define GC_REV			0x00008084
 #define GC_GEO_FIFO		0x00008400
 
 typedef struct {
@@ -106,6 +110,7 @@ typedef struct {
 	unsigned int value;
 } gdc_regs;
 
+int mb862xx_probe(unsigned int addr);
 const gdc_regs *board_get_regs (void);
 unsigned int board_video_init (void);
 void board_backlight_switch(int);