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@@ -369,7 +369,8 @@ flush_dcache:
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
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/*
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/*
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- * disable MMU and D cache, and enable I cache
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+ * disable MMU and D cache
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+ * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
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*/
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*/
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mrc p15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
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bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
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@@ -380,7 +381,9 @@ flush_dcache:
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bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
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bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
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#endif
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#endif
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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+#ifndef CONFIG_SYS_ICACHE_OFF
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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+#endif
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c1, c0, 0
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/*
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/*
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