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@@ -188,6 +188,21 @@ int cpu_init_r (void)
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volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
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volatile uint temp;
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+ asm("msync;isync");
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+ temp = l2cache->l2ctl;
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+ temp &= 0x30000000;
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+ switch ( temp ) {
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+ case 0x20000000:
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+ printf ("L2 cache 256KB:");
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+ break;
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+ case 0x00000000:
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+ case 0x10000000:
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+ case 0x30000000:
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+ default:
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+ printf ("L2 cache unknown size. Check the silicon!\n");
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+ return -1;
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+ }
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+
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asm("msync;isync");
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l2cache->l2ctl = 0x68000000; /* invalidate */
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temp = l2cache->l2ctl;
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@@ -196,7 +211,7 @@ int cpu_init_r (void)
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temp = l2cache->l2ctl;
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asm("msync;isync");
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- printf("L2: 256 kB enabled\n");
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+ printf("enabled\n");
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#else
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printf("L2: disabled.\n");
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#endif
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