Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  mpc85xx: support for Freescale COM Express P2020
  arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
  mpc85xx: support board-specific reset function
  powerpc/85xx: verify the localbus device tree address before booting the OS
  mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
  powerpc/p3060qds: Add board related support for P3060QDS platform
  powerpc/85xx: clean up and document the QE/FMAN microcode macros
  powerpc/85xx: always implement the work-around for Erratum SATA_A001
  powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
  powerpc/85xx: Add workaround for erratum A-003474
  powerpc/85xx: fixup flexcan device tree clock-frequency
  powerpc/85xx: Add workaround for erratum CPU-A003999

MAINTAINERS

@@ -450,6 +450,10 @@ Jon Smirl <jonsmirl@gmail.com>
 
 	pcm030		MPC5200
 
+Ira W. Snyder <iws@ovro.caltech.edu>
+
+	P2020COME	P2020
+
 Timur Tabi <timur@freescale.com>
 
 	MPC8349E-mITX	MPC8349

README

@@ -3274,6 +3274,44 @@ Low Level (hardware related) configuration options:
 		be used if available. These functions may be faster under some
 		conditions but may increase the binary size.
 
+Freescale QE/FMAN Firmware Support:
+-----------------------------------
+
+The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
+loading of "firmware", which is encoded in the QE firmware binary format.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_SYS_QE_FMAN_FW_ADDR
+	The address in the storage device where the firmware is located.  The
+	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+	is also specified.
+
+- CONFIG_SYS_QE_FMAN_FW_LENGTH
+	The maximum possible size of the firmware.  The firmware binary format
+	has a field that specifies the actual size of the firmware, but it
+	might not be possible to read any part of the firmware unless some
+	local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NOR
+	Specifies that QE/FMAN firmware is located in NOR flash, mapped as
+	normal addressable memory via the LBC.  CONFIG_SYS_FMAN_FW_ADDR is the
+	virtual address in NOR flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NAND
+	Specifies that QE/FMAN firmware is located in NAND flash.
+	CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_MMC
+	Specifies that QE/FMAN firmware is located on the primary SD/MMC
+	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+	Specifies that QE/FMAN firmware is located on the primary SPI
+	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+
 Building the Software:
 ======================
 

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -53,6 +53,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
 	puts("Work-around for Erratum CPU22 enabled\n");
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
+	puts("Work-around for Erratum CPU-A003999 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
+	puts("Work-around for Erratum DDR-A003473 enabled\n");
+#endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
 #endif

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -42,6 +42,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Default board reset function
+ */
+static void
+__board_reset(void)
+{
+	/* Do nothing */
+}
+void board_reset(void) __attribute__((weak, alias("__board_reset")));
+
 int checkcpu (void)
 {
 	sys_info_t sysinfo;
@@ -215,7 +225,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	mtspr(DBCR0,val);
 #else
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	out_be32(&gur->rstcr, 0x2);	/* HRESET_REQ */
+
+	/* Attempt board-specific reset */
+	board_reset();
+
+	/* Next try asserting HRESET_REQ */
+	out_be32(&gur->rstcr, 0x2);
 	udelay(100);
 #endif
 

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -37,12 +37,15 @@
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
+#include <linux/compiler.h>
 #include "mp.h"
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
 #endif
 
+#include "../../../../drivers/block/fsl_sata.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void srio_init(void);
@@ -301,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
  */
 int cpu_init_r(void)
 {
+	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_SYS_LBC_LCRR
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
@@ -316,10 +320,9 @@ int cpu_init_r(void)
 #if defined(CONFIG_L2_CACHE)
 	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
-	uint svr, ver;
+	uint ver;
 	u32 l2siz_field;
 
-	svr = get_svr();
 	ver = SVR_SOC_VER(svr);
 
 	asm("msync;isync");
@@ -401,8 +404,8 @@ int cpu_init_r(void)
 		puts("enabled\n");
 	}
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
-	if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
-	    (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+	if ((SVR_SOC_VER(svr) == SVR_P2040) ||
+	    (SVR_SOC_VER(svr) == SVR_P2040_E)) {
 		puts("N/A\n");
 		goto skip_l2;
 	}
@@ -488,6 +491,32 @@ skip_l2:
 	fman_enet_init();
 #endif
 
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+	/*
+	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
+	 * controller is configured in legacy mode instead of the
+	 * expected enterprise mode. Software needs to clear bit[28]
+	 * of HControl register to change to enterprise mode from
+	 * legacy mode.  We assume that the controller is offline.
+	 */
+	if (IS_SVR_REV(svr, 1, 0) &&
+	    ((SVR_SOC_VER(svr) == SVR_P1022) ||
+	     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
+	     (SVR_SOC_VER(svr) == SVR_P1013) ||
+	     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+		fsl_sata_reg_t *reg;
+
+		/* first SATA controller */
+		reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
+
+		/* second SATA controller */
+		reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
+	}
+#endif
+
+
 	return 0;
 }
 
@@ -523,17 +552,17 @@ void cpu_secondary_init_r(void)
 {
 #ifdef CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 	int ret;
-	size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
 
 	/* load QE firmware from NAND flash to DDR first */
-	ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
-			&fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+	ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
+			&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
 
 	if (ret && ret == -EUCLEAN) {
 		printf ("NAND read for QE firmware at offset %x failed %d\n",
-				CONFIG_SYS_QE_FW_IN_NAND, ret);
+				CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
 	}
 #endif
 	qe_init(qe_base);

arch/powerpc/cpu/mpc85xx/ddr-gen3.c

@@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	for (i = 0; i < 32; i++)
 		out_be32(&ddr->debug[i], regs->debug[i]);
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+	out_be32(&ddr->debug[12], 0x00000015);
+	out_be32(&ddr->debug[21], 0x24000000);
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+
 	/* Set, but do not enable the memory */
 	temp_sdram_cfg = regs->ddr_sdram_cfg;
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);

arch/powerpc/cpu/mpc85xx/fdt.c

@@ -466,7 +466,7 @@ void fdt_fixup_fman_firmware(void *blob)
 		return;
 	}
 
-	if (length > CONFIG_SYS_FMAN_FW_LENGTH) {
+	if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
 		printf("Fman firmware at %p is too large (size=%u)\n",
 		       fmanfw, length);
 		return;
@@ -660,8 +660,19 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
 			"timer-frequency", gd->bus_clk/2, 1);
 
+	/*
+	 * clock-freq should change to clock-frequency and
+	 * flexcan-v1.0 should change to p1010-flexcan respectively
+	 * in the future.
+	 */
 	do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
-			"clock_freq", gd->bus_clk, 1);
+			"clock_freq", gd->bus_clk/2, 1);
+
+	do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
+			"clock-frequency", gd->bus_clk/2, 1);
+
+	do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
+			"clock-frequency", gd->bus_clk/2, 1);
 
 	fdt_fixup_usb(blob);
 }
@@ -677,6 +688,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #define CCSR_VIRT_TO_PHYS(x) \
 	(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
 
+static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
+{
+	printf("Warning: U-Boot configured %s at address %llx,\n"
+	       "but the device tree has it at %llx\n", name, uaddr, daddr);
+}
+
 /*
  * Verify the device tree
  *
@@ -692,33 +709,32 @@ void ft_cpu_setup(void *blob, bd_t *bd)
  */
 int ft_verify_fdt(void *fdt)
 {
-	uint64_t ccsr = 0;
+	uint64_t addr = 0;
 	int aliases;
 	int off;
 
 	/* First check the CCSR base address */
 	off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
 	if (off > 0)
-		ccsr = fdt_get_base_address(fdt, off);
+		addr = fdt_get_base_address(fdt, off);
 
-	if (!ccsr) {
+	if (!addr) {
 		printf("Warning: could not determine base CCSR address in "
 		       "device tree\n");
 		/* No point in checking anything else */
 		return 0;
 	}
 
-	if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
-		printf("Warning: U-Boot configured CCSR at address %llx,\n"
-		       "but the device tree has it at %llx\n",
-		       (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
+	if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
+		msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
 		/* No point in checking anything else */
 		return 0;
 	}
 
 	/*
-	 * Get the 'aliases' node.  If there isn't one, then there's nothing
-	 * left to do.
+	 * Check some nodes via aliases.  We assume that U-Boot and the device
+	 * tree enumerate the devices equally.  E.g. the first serial port in
+	 * U-Boot is the same as "serial0" in the device tree.
 	 */
 	aliases = fdt_path_offset(fdt, "/aliases");
 	if (aliases > 0) {
@@ -735,5 +751,30 @@ int ft_verify_fdt(void *fdt)
 #endif
 	}
 
+	/*
+	 * The localbus node is typically a root node, even though the lbc
+	 * controller is part of CCSR.  If we were to put the lbc node under
+	 * the SOC node, then the 'ranges' property in the lbc node would
+	 * translate through the 'ranges' property of the parent SOC node, and
+	 * we don't want that.  Since it's a separate node, it's possible for
+	 * the 'reg' property to be wrong, so check it here.  For now, we
+	 * only check for "fsl,elbc" nodes.
+	 */
+#ifdef CONFIG_SYS_LBC_ADDR
+	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
+	if (off > 0) {
+		const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
+		if (reg) {
+			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
+
+			addr = fdt_translate_address(fdt, off, reg);
+			if (uaddr != addr) {
+				msg("the localbus", uaddr, addr);
+				return 0;
+			}
+		}
+	}
+#endif
+
 	return 1;
 }

arch/powerpc/cpu/mpc85xx/release.S

@@ -68,6 +68,12 @@ __secondary_start_page:
 	mtspr	SPRN_HID1,r3
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+	mfspr	r3,977
+	oris	r3,r3,0x0100
+	mtspr	977,r3
+#endif
+
 	/* Enable branch prediction */
 	lis	r3,BUCSR_ENABLE@h
 	ori	r3,r3,BUCSR_ENABLE@l

arch/powerpc/cpu/mpc85xx/start.S

@@ -253,6 +253,12 @@ l2_disabled:
 	mtspr	HID1,r0
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+	mfspr	r3,977
+	oris	r3,r3,0x0100
+	mtspr	977,r3
+#endif
+
 	/* Enable Branch Prediction */
 #if defined(CONFIG_BTB)
 	lis	r0,BUCSR_ENABLE@h

arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c

@@ -135,6 +135,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
 	case DDR3_SPD_MODULETYPE_RDIMM:
 	case DDR3_SPD_MODULETYPE_MINI_RDIMM:
+	case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
 		/* Registered/buffered DIMMs */
 		pdimm->registered_dimm = 1;
 		for (i = 0; i < 16; i += 2) {
@@ -148,6 +149,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	case DDR3_SPD_MODULETYPE_SO_DIMM:
 	case DDR3_SPD_MODULETYPE_MICRO_DIMM:
 	case DDR3_SPD_MODULETYPE_MINI_UDIMM:
+	case DDR3_SPD_MODULETYPE_MINI_CDIMM:
+	case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
+	case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
+	case DDR3_SPD_MODULETYPE_LRDIMM:
+	case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
+	case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
 		/* Unbuffered DIMMs */
 		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
 			pdimm->mirrored_dimm = 1;

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c

@@ -1354,7 +1354,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 {
 	unsigned long long ddrsize;
 	const char *prompt = "FSL DDR>";
-	unsigned int len;
 	char buffer[CONFIG_SYS_CBSIZE];
 	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
 	int argc;
@@ -1389,7 +1388,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 		 * No need to worry for buffer overflow here in
 		 * this function;  readline() maxes out at CFG_CBSIZE
 		 */
-		len = readline_into_buffer(prompt,  buffer);
+		readline_into_buffer(prompt,  buffer);
 		argc = parse_line(buffer, argv);
 		if (argc == 0)
 			continue;

arch/powerpc/include/asm/config_mpc85xx.h

@@ -150,6 +150,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -237,6 +238,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -313,12 +315,15 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P2041)
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
@@ -331,12 +336,15 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
@@ -349,6 +357,8 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P3060)
 #define CONFIG_MAX_CPUS			8
@@ -364,6 +374,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS			4
@@ -374,6 +385,8 @@
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -402,6 +415,8 @@
 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 /* P5010 is single core version of P5020 */
 #elif defined(CONFIG_PPC_P5010)
@@ -409,6 +424,7 @@
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
@@ -421,12 +437,14 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P5020)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
@@ -439,6 +457,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #else
 #error Processor type not defined for this platform

arch/powerpc/include/asm/immap_85xx.h

@@ -2420,6 +2420,7 @@ struct ccsr_rman {
 #define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		0x22000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
 #else

board/freescale/common/Makefile

@@ -34,6 +34,7 @@ COBJS-$(CONFIG_FSL_VIA)		+= cds_via.o
 COBJS-$(CONFIG_FMAN_ENET)	+= fman.o
 COBJS-$(CONFIG_FSL_PIXIS)	+= pixis.o
 COBJS-$(CONFIG_FSL_NGPIXIS)	+= ngpixis.o
+COBJS-$(CONFIG_FSL_QIXIS)	+= qixis.o
 COBJS-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
 COBJS-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
 COBJS-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
@@ -50,12 +51,14 @@ COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
 COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
+COBJS-$(CONFIG_P3060QDS)       	+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
 
 # deal with common files for P-series corenet based devices
 SUBLIB-$(CONFIG_P2041RDB)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P3060QDS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
 

board/freescale/common/ics307_clk.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,10 +25,15 @@
 
 #include "ics307_clk.h"
 
-#ifdef CONFIG_FSL_NGPIXIS
+#if defined(CONFIG_FSL_NGPIXIS)
 #include "ngpixis.h"
+#define fpga_reg pixis
+#elif defined(CONFIG_FSL_QIXIS)
+#include "qixis.h"
+#define fpga_reg ((struct qixis *)QIXIS_BASE)
 #else
 #include "pixis.h"
+#define fpga_reg pixis
 #endif
 
 /* define for SYS CLK or CLK1Frequency */
@@ -143,15 +148,15 @@ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
 unsigned long get_board_sys_clk(void)
 {
 	return ics307_clk_freq(
-			in_8(&pixis->sclk[0]),
-			in_8(&pixis->sclk[1]),
-			in_8(&pixis->sclk[2]));
+			in_8(&fpga_reg->sclk[0]),
+			in_8(&fpga_reg->sclk[1]),
+			in_8(&fpga_reg->sclk[2]));
 }
 
 unsigned long get_board_ddr_clk(void)
 {
 	return ics307_clk_freq(
-			in_8(&pixis->dclk[0]),
-			in_8(&pixis->dclk[1]),
-			in_8(&pixis->dclk[2]));
+			in_8(&fpga_reg->dclk[0]),
+			in_8(&fpga_reg->dclk[1]),
+			in_8(&fpga_reg->dclk[2]));
 }

board/freescale/common/qixis.c

@@ -0,0 +1,151 @@
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "qixis.h"
+
+u8 qixis_read(unsigned int reg)
+{
+	void *p = (void *)QIXIS_BASE;
+
+	return in_8(p + reg);
+}
+
+void qixis_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)QIXIS_BASE;
+
+	out_8(p + reg, value);
+}
+
+void qixis_reset(void)
+{
+	QIXIS_WRITE(rst_ctl, 0x83);
+}
+
+void qixis_bank_reset(void)
+{
+	QIXIS_WRITE(rcfg_ctl, 0x20);
+	QIXIS_WRITE(rcfg_ctl, 0x21);
+}
+
+/* Set the boot bank to the power-on default bank0 */
+void clear_altbank(void)
+{
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[0]);
+	reg = reg & ~QIXIS_LBMAP_MASK;
+	QIXIS_WRITE(brdcfg[0], reg);
+}
+
+/* Set the boot bank to the alternate bank */
+void set_altbank(void)
+{
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[0]);
+	reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
+	QIXIS_WRITE(brdcfg[0], reg);
+}
+
+#ifdef DEBUG
+static void qixis_dump_regs(void)
+{
+	int i;
+
+	printf("id	= %02x\n", QIXIS_READ(id));
+	printf("arch	= %02x\n", QIXIS_READ(arch));
+	printf("scver	= %02x\n", QIXIS_READ(scver));
+	printf("model	= %02x\n", QIXIS_READ(model));
+	printf("rst_ctl	= %02x\n", QIXIS_READ(rst_ctl));
+	printf("aux	= %02x\n", QIXIS_READ(aux));
+	for (i = 0; i < 16; i++)
+		printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
+	for (i = 0; i < 16; i++)
+		printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
+	printf("sclk	= %02x%02x%02x\n", QIXIS_READ(sclk[0]),
+		QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
+	printf("dclk	= %02x%02x%02x\n", QIXIS_READ(dclk[0]),
+		QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
+	printf("aux     = %02x\n", QIXIS_READ(aux));
+	printf("watch	= %02x\n", QIXIS_READ(watch));
+	printf("ctl_sys	= %02x\n", QIXIS_READ(ctl_sys));
+	printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
+	printf("present = %02x\n", QIXIS_READ(present));
+	printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
+	printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
+	printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
+	printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
+	printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2));
+}
+#endif
+
+int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+
+	if (argc <= 1) {
+		clear_altbank();
+		qixis_reset();
+	} else if (strcmp(argv[1], "altbank") == 0) {
+		set_altbank();
+		qixis_bank_reset();
+	} else if (strcmp(argv[1], "watchdog") == 0) {
+		static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
+					  "1min", "2min", "4min", "8min"};
+		u8 rcfg = QIXIS_READ(rcfg_ctl);
+
+		if (argv[2] == NULL) {
+			printf("qixis watchdog <watchdog_period>\n");
+			return 0;
+		}
+		for (i = 0; i < ARRAY_SIZE(period); i++) {
+			if (strcmp(argv[2], period[i]) == 0) {
+				/* disable watchdog */
+				QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
+				QIXIS_WRITE(watch, ((i<<2) - 1));
+				QIXIS_WRITE(rcfg_ctl, rcfg);
+				return 0;
+			}
+		}
+	}
+
+#ifdef DEBUG
+	else if (strcmp(argv[1], "dump") == 0) {
+		qixis_dump_regs();
+		return 0;
+	}
+#endif
+
+	else {
+		printf("Invalid option: %s\n", argv[1]);
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
+	"Reset the board using the FPGA sequencer",
+	"- hard reset to default bank\n"
+	"qixis_reset altbank - reset to alternate bank\n"
+	"qixis watchdog <watchdog_period> - set the watchdog period\n"
+	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
+#ifdef DEBUG
+	"qixis_reset dump - display the QIXIS registers\n"
+#endif
+	);

board/freescale/common/qixis.h

@@ -0,0 +1,101 @@
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ */
+
+#ifndef __QIXIS_H_
+#define __QIXIS_H_
+
+struct qixis {
+	u8 id;      /* ID value uniquely identifying each QDS board type */
+	u8 arch;    /* Board version information */
+	u8 scver;   /* QIXIS Version Register */
+	u8 model;   /* Information of software programming model version */
+	u8 tagdata;
+	u8 ctl_sys;
+	u8 aux;         /* Auxiliary Register,0x06 */
+	u8 clk_spd;
+	u8 stat_dut;
+	u8 stat_sys;
+	u8 stat_alrm;
+	u8 present;
+	u8 ctl_sys2;
+	u8 rcw_ctl;
+	u8 ctl_led;
+	u8 i2cblk;
+	u8 rcfg_ctl;    /* Reconfig Control Register,0x10 */
+	u8 rcfg_st;
+	u8 dcm_ad;
+	u8 dcm_da;
+	u8 dcmd;
+	u8 dmsg;
+	u8 gdc;
+	u8 gdd;         /* DCM Debug Data Register,0x17 */
+	u8 dmack;
+	u8 res1[6];
+	u8 watch;       /* Watchdog Register,0x1F */
+	u8 pwr_ctl[2];  /* Power Control Register,0x20 */
+	u8 res2[2];
+	u8 pwr_stat[4]; /* Power Status Register,0x24 */
+	u8 res3[8];
+	u8 clk_spd2[2];  /* SYSCLK clock Speed Register,0x30 */
+	u8 res4[2];
+	u8 sclk[3];  /* Clock Configuration Registers,0x34 */
+	u8 res5;
+	u8 dclk[3];
+	u8 res6;
+	u8 clk_dspd[3];
+	u8 res7;
+	u8 rst_ctl;     /* Reset Control Register,0x40 */
+	u8 rst_stat;    /* Reset Status Register */
+	u8 rst_rsn;     /* Reset Reason Register */
+	u8 rst_frc[2];  /* Reset Force Registers,0x43 */
+	u8 res8[11];
+	u8 brdcfg[16];  /* Board Configuration Register,0x50 */
+	u8 dutcfg[16];
+	u8 rcw_ad[2];   /* RCW SRAM Address Registers,0x70 */
+	u8 rcw_data;
+	u8 res9[5];
+	u8 post_ctl;
+	u8 post_stat;
+	u8 post_dat[2];
+	u8 pi_d[4];
+	u8 gpio_io[4];
+	u8 gpio_dir[4];
+	u8 res10[20];
+	u8 rjtag_ctl;
+	u8 rjtag_dat;
+	u8 res11[2];
+	u8 trig_src[4];
+	u8 trig_dst[4];
+	u8 trig_stat;
+	u8 res12[3];
+	u8 trig_ctr[4];
+	u8 res13[48];
+	u8 aux2[4];	/* Auxiliary Registers,0xE0 */
+	u8 res14[10];
+	u8 aux_ad;
+	u8 aux_da;
+	u8 res15[16];
+};
+
+#define QIXIS_BASE		0xffdf0000
+#define QIXIS_LBMAP_SWITCH	7
+#define QIXIS_LBMAP_MASK	0x0f
+#define QIXIS_LBMAP_SHIFT	0
+#define QIXIS_LBMAP_ALTBANK	0x04
+
+u8 qixis_read(unsigned int reg);
+void qixis_write(unsigned int reg, u8 value);
+
+#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+
+#endif

board/freescale/p2020come/Makefile

@@ -0,0 +1,46 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB			= $(obj)lib$(BOARD).o
+
+COBJS-y			+= $(BOARD).o
+COBJS-y			+= ddr.o
+COBJS-y			+= law.o
+COBJS-y			+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/p2020come/ddr.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * Set DDR_SDRAM_CLK_CNTL = 0x02800000
+	 *
+	 * Clock is launched 5/8 applied cycle after address/command
+	 */
+	popts->clk_adjust = 5;
+}

board/freescale/p2020come/law.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
+ * the DDR SPD setup code runs.
+ *
+ * This table would be empty, except that it is used before the BSS section is
+ * initialized, and therefore must have at least one entry to push it into
+ * the DATA section.
+ */
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/p2020come/p2020come.c

@@ -0,0 +1,287 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/mpc85xx_gpio.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_PCI)
+#include <asm/fsl_pci.h>
+#include <pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void ft_pci_board_setup(void *blob)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
+
+#define BOARD_PERI_RST_SET	(VSC7385_RST_SET | SLIC_RST_SET | \
+				 SGMII_PHY_RST_SET | PCIE_RST_SET | \
+				 RGMII_PHY_RST_SET)
+
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+#define BOARDREV_B	0x10100000
+#define BOARDREV_C	0x00100000
+#define BOARDREV_D	0x00000000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_50	50000000
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+	switch (ddr_ratio) {
+	case 0x0C:
+		return SYSCLK_66;
+	case 0x0A:
+	case 0x08:
+		return SYSCLK_100;
+	default:
+		puts("ERROR: unknown DDR ratio\n");
+		return SYSCLK_100;
+	}
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+	switch (ddr_ratio) {
+	case 0x0C:
+	case 0x0A:
+		return SYSCLK_66;
+	case 0x08:
+		return SYSCLK_100;
+	default:
+		puts("ERROR: unknown DDR ratio\n");
+		return SYSCLK_100;
+	}
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD |
+			 MPC85xx_PMUXCR_SDHC_WP));
+
+	/* All the device are enable except for SRIO12 */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
+	return 0;
+}
+#endif
+
+#define GPIO_DIR		0x0f3a0000
+#define GPIO_ODR		0x00000000
+#define GPIO_DAT		0x001a0000
+
+int checkboard(void)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
+
+	/*
+	 * GPIO
+	 * 0 - 3: CarryBoard Input;
+	 * 4 - 7: CarryBoard Output;
+	 * 8 : Mux as SDHC_CD (card detection)
+	 * 9 : Mux as SDHC_WP
+	 * 10 : Clear Watchdog timer
+	 * 11 : LED Input
+	 * 12 : Output to 1
+	 * 13 : Open Drain
+	 * 14 : LED Output
+	 * 15 : Switch Input
+	 *
+	 * Set GPIOs 11, 12, 14 to 1.
+	 */
+	out_be32(&pgpio->gpodr, GPIO_ODR);
+	mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
+
+	puts("Board: Freescale COM Express P2020\n");
+	return 0;
+}
+
+#define M41ST85W_I2C_BUS	1
+#define M41ST85W_I2C_ADDR	0x68
+#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
+
+static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
+{
+	u8 data;
+
+	if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
+		M41ST85W_ERROR("unable to read %s bit\n", name);
+		return;
+	}
+
+	if (data & mask) {
+		data &= ~mask;
+		if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
+			M41ST85W_ERROR("unable to clear %s bit\n", name);
+			return;
+		}
+	}
+}
+
+#define M41ST85W_REG_SEC2	0x01
+#define M41ST85W_REG_SEC2_ST	0x80
+
+#define M41ST85W_REG_ALHOUR	0x0c
+#define M41ST85W_REG_ALHOUR_HT	0x40
+
+/*
+ * The P2020COME board has a STMicro M41ST85W RTC/watchdog
+ * at i2c bus 1 address 0x68.
+ */
+static void start_rtc(void)
+{
+	unsigned int bus = i2c_get_bus_num();
+
+	if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
+		M41ST85W_ERROR("unable to set i2c bus\n");
+		goto out;
+	}
+
+	/* ensure ST (stop) and HT (halt update) bits are cleared */
+	m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
+	m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
+
+out:
+	/* reset the i2c bus */
+	i2c_set_bus_num(bus);
+}
+
+int board_early_init_r(void)
+{
+	start_rtc();
+	return 0;
+}
+
+#define M41ST85W_REG_WATCHDOG		0x09
+#define M41ST85W_REG_WATCHDOG_WDS	0x80
+#define M41ST85W_REG_WATCHDOG_BMB0	0x04
+
+void board_reset(void)
+{
+	u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
+
+	/* set the hardware watchdog timeout to 1/16 second, then hang */
+	i2c_set_bus_num(M41ST85W_I2C_BUS);
+	i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
+
+	while (1)
+		/* hang */;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+	ft_pci_board_setup(blob);
+#endif
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif

board/freescale/p2020come/tlb.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+			MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+			MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+			MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+			MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_PCI)
+	/* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 2, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+			CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI I/O
+	 *
+	 * PCI3 => 0xFFC10000
+	 * PCI2 => 0xFFC2,0000
+	 * PCI1 => 0xFFC3,0000
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_256K, 1),
+#endif /* #if defined(CONFIG_PCI) */
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/freescale/p3060qds/Makefile

@@ -0,0 +1,54 @@
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += eth.o
+COBJS-y += fixed_ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/p3060qds/ddr.c

@@ -0,0 +1,248 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+#include "p3060qds.h"
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	unsigned int lawbar1_target_id;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs,
+				fixed_ddr_parm_0[i].ddr_settings,
+				sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+			strmhz(buf, ddr_freq));
+
+	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+	/*
+	 * setup laws for DDR. If not interleaving, presuming half memory on
+	 * DDR1 and the other half on DDR2
+	 */
+	if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size,
+				 LAW_TRGT_IF_DDR_INTRLV) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+	} else {
+		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+	}
+	return ddr_size;
+}
+
+struct board_specific_params {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_params udimm[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |      |delay |
+	 */
+	{4,   850,    4,     6,   0xff,    2,  0},
+	{4,   950,    5,     7,   0xff,    2,  0},
+	{4,  1050,    5,     8,   0xff,    2,  0},
+	{4,  1250,    5,    10,   0xff,    2,  0},
+	{4,  1350,    5,    11,   0xff,    2,  0},
+	{4,  1666,    5,    12,   0xff,    2,  0},
+	{2,   850,    5,     6,   0xff,    2,  0},
+	{2,   950,    5,     7,   0xff,    2,  0},
+	{2,  1250,    4,     6,   0xff,    2,  0},
+	{2,  1350,    5,     7,   0xff,    2,  0},
+	{2,  1666,    5,     8,   0xff,    2,  0},
+	{1,   850,    4,     5,   0xff,    2,  0},
+	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1666,    4,     8,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_params rdimm[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |      |delay |
+	 */
+	{4,   850,    4,     6,   0xff,    2,  0},
+	{4,   950,    5,     7,   0xff,    2,  0},
+	{4,  1050,    5,     8,   0xff,    2,  0},
+	{4,  1250,    5,    10,   0xff,    2,  0},
+	{4,  1350,    5,    11,   0xff,    2,  0},
+	{4,  1666,    5,    12,   0xff,    2,  0},
+	{2,   850,    4,     6,   0xff,    2,  0},
+	{2,  1050,    4,     7,   0xff,    2,  0},
+	{2,  1666,    4,     8,   0xff,    2,  0},
+	{1,   850,    4,     5,   0xff,    2,  0},
+	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1666,    4,     8,   0xff,    2,  0},
+	{}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_params *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	if (popts->registered_dimm_en)
+		pbsp = rdimm;
+	else
+		pbsp = udimm;
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->twoT_en = pbsp->force_2T;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s!\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->twoT_en = pbsp_highest->force_2T;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+
+
+found:
+
+	/*
+	 * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
+	 * However SPD still claims CL=7 is supported. Extensive tests
+	 * confirmed this board cannot work stably with CL=7 with this
+	 * particular DIMM.
+	 */
+	if (ddr_freq >= 800 && ddr_freq < 1066 && \
+		!strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
+		popts->cas_latency_override = 1;
+		popts->cas_latency_override_value = 8;
+		debug("Override CL to 8\n");
+	}
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 60 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....");
+
+	if (fsl_use_spd()) {
+		puts("using SPD\n");
+		dram_size = fsl_ddr_sdram();
+	} else {
+		puts("using fixed parameters\n");
+		dram_size = fixed_sdram();
+	}
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	debug("    DDR: ");
+	return dram_size;
+}

board/freescale/p3060qds/eth.c

@@ -0,0 +1,482 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+
+#include "p3060qds_qixis.h"
+
+#define EMI_NONE       0xffffffff
+#define EMI1_RGMII1    0
+#define EMI1_SLOT1     1
+#define EMI1_SLOT2     2
+#define EMI1_SLOT3     3
+#define EMI1_RGMII2    4
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static char *mdio_names[5] = {
+	"P3060QDS_MDIO0",
+	"P3060QDS_MDIO1",
+	"P3060QDS_MDIO2",
+	"P3060QDS_MDIO3",
+	"P3060QDS_MDIO4",
+};
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots.
+ * A value of '0' here means that the mapping must be determined
+ * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
+ */
+static u8 lane_to_slot[] = {
+	4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
+};
+
+static char *p3060qds_mdio_name_for_muxval(u32 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u32 muxval)
+{
+	struct mii_dev *bus;
+	char *name = p3060qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct p3060qds_mdio {
+	u32 muxval;
+	struct mii_dev *realbus;
+};
+
+static void p3060qds_mux_mdio(u32 muxval)
+{
+	u8 brdcfg4;
+
+	brdcfg4 = QIXIS_READ(brdcfg[4]);
+	brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+	brdcfg4 |= (muxval << 4);
+	QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct p3060qds_mdio *priv = bus->priv;
+
+	p3060qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct p3060qds_mdio *priv = bus->priv;
+
+	p3060qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int p3060qds_mdio_reset(struct mii_dev *bus)
+{
+	struct p3060qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int p3060qds_mdio_init(char *realbusname, u32 muxval)
+{
+	struct p3060qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate P3060QDS MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate P3060QDS private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = p3060qds_mdio_read;
+	bus->write = p3060qds_mdio_write;
+	bus->reset = p3060qds_mdio_reset;
+	sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+				enum fm_port port, int offset)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+			  FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	if (mdio_mux[port] == EMI1_RGMII1)
+		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
+
+	if (mdio_mux[port] == EMI1_RGMII2)
+		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
+
+	if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
+		|| (srds_prtcl == 0x6))) {
+		switch (port) {
+		case FM2_DTSEC4:
+			fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
+			break;
+		case FM1_DTSEC4:
+			fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (mdio_mux[port] == EMI1_SLOT3) {
+		switch (port) {
+		case FM2_DTSEC3:
+			fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
+			break;
+		case FM1_DTSEC3:
+			fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i, lane, idx;
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT1:
+				if (lane >= 14) {
+					fdt_status_okay_by_alias(fdt,
+						"emi1_slot1");
+					fdt_status_disabled_by_alias(fdt,
+						"emi1_slot1_bk1");
+				} else {
+					fdt_status_disabled_by_alias(fdt,
+						"emi1_slot1");
+					fdt_status_okay_by_alias(fdt,
+						"emi1_slot1_bk1");
+				}
+				break;
+			case EMI1_SLOT2:
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+				break;
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+				break;
+			}
+		break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC1)
+				fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+
+			if (i == FM1_DTSEC2)
+				fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
+			break;
+		default:
+			break;
+		}
+	}
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		idx = i - FM2_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+			if (lane >= 0) {
+				switch (mdio_mux[i]) {
+				case EMI1_SLOT1:
+					if (lane >= 14)
+						fdt_status_okay_by_alias(fdt,
+							"emi1_slot1");
+					else
+						fdt_status_okay_by_alias(fdt,
+							"emi1_slot1_bk1");
+					break;
+				case EMI1_SLOT2:
+					fdt_status_okay_by_alias(fdt,
+						"emi1_slot2");
+					break;
+				case EMI1_SLOT3:
+					fdt_status_okay_by_alias(fdt,
+						"emi1_slot3");
+					break;
+				}
+			}
+			break;
+		default:
+			break;
+		}
+	}
+#endif
+}
+
+static void initialize_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int sdprtl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	switch (sdprtl) {
+	case 0x03:
+	case 0x06:
+		lane_to_slot[8] = 1;
+		lane_to_slot[9] = lane_to_slot[8];
+		lane_to_slot[16] = 5;
+		lane_to_slot[17] = lane_to_slot[16];
+		break;
+	case 0x16:
+	case 0x19:
+	case 0x1C:
+		lane_to_slot[8] = 5;
+		lane_to_slot[9] = lane_to_slot[8];
+		lane_to_slot[16] = 1;
+		lane_to_slot[17] = lane_to_slot[16];
+		break;
+	default:
+		puts("Invalid SerDes protocol for P3060QDS\n");
+		break;
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
+	int i;
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int srds_cfg = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	initialize_lane_to_slot();
+
+	/*
+	 * Set TBIPA on FM1@DTSEC1.  This is needed for configurations
+	 * where FM1@DTSEC1 isn't used directly, since it provides
+	 * MDIO for other ports.
+	 */
+	out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	/* Register the 5 muxing front-ends to the MDIO buses */
+	if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
+		p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+
+	if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
+		p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+
+	if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
+		fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
+	else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
+
+	if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
+		fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
+	else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+
+	fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
+
+	switch (srds_cfg) {
+	case 0x03:
+	case 0x06:
+		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0x16:
+	case 0x19:
+	case 0x1C:
+		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	default:
+		puts("Invalid SerDes protocol for P3060QDS\n");
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			if (QIXIS_READ(present) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC1) {
+				mdio_mux[i] = EMI1_RGMII1;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+			} else if (i == FM1_DTSEC2) {
+				mdio_mux[i] = EMI1_RGMII2;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		int idx = i - FM2_DTSEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			if (QIXIS_READ(present) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		default:
+			break;
+		}
+	}
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}

board/freescale/p3060qds/fixed_ddr.c

@@ -0,0 +1,214 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#define CONFIG_SYS_DDR_TIMING_3_1200	0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200	0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200	0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200	0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200	0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200	0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200	0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000	0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000	0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000	0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000	0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000	0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000	0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900	0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900	0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900	0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900	0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900	0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900	0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800	0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS		0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS		0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS	0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS	0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS	0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG	0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG	0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG	0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x24401031
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{750, 850, &ddr_cfg_regs_800},
+	{850, 950, &ddr_cfg_regs_900},
+	{950, 1050, &ddr_cfg_regs_1000},
+	{1050, 1250, &ddr_cfg_regs_1200},
+	{0, 0, NULL}
+};

board/freescale/p3060qds/p3060qds.c

@@ -0,0 +1,341 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <configs/P3060QDS.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/qixis.h"
+#include "p3060qds.h"
+#include "p3060qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->cpu;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	unsigned int i;
+
+	printf("Board: %s", cpu->name);
+	puts("QDS, ");
+
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+#ifdef CONFIG_PHYS_64BIT
+	puts("36-bit Addressing\n");
+#endif
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
+	puts("SERDES Reference Clocks: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < 3; i++) {
+		static const char * const freq[] = {"100", "125", "Reserved",
+						"156.25"};
+		unsigned int clock = (sw >> (2 * i)) & 3;
+
+		printf("Bank%u=%sMhz ", i+1, freq[clock]);
+	}
+	puts("\n");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
+	setbits_be32(&gur->ddrclkdr, 0x00030000);
+
+	return 0;
+}
+
+void board_config_serdes_mux(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int cfg = (in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	switch (cfg) {
+	case 0x03:
+	case 0x06:
+		/* set Lane I,J as SGMII */
+		QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
+				       BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
+		break;
+	case 0x16:
+	case 0x19:
+	case 0x1c:
+		/* set Lane I,J as Aurora Debug */
+		QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
+				       BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
+		break;
+	default:
+		puts("Invalid SerDes protocol for P3060QDS\n");
+		break;
+	}
+}
+
+void board_config_usb_mux(void)
+{
+	u8 brdcfg4, brdcfg5, brdcfg7;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
+	u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
+	u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
+
+	brdcfg4 = QIXIS_READ(brdcfg[4]);
+	brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
+	if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
+		 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
+		brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
+
+	} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
+		 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
+		 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
+		brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
+
+	} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
+		 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
+		brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
+
+	} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
+		 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
+		 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
+		brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
+	} else {
+		brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
+	}
+	QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+	brdcfg5 = QIXIS_READ(brdcfg[5]);
+	brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
+	brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
+	QIXIS_WRITE(brdcfg[5], brdcfg5);
+
+	brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
+		BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
+	QIXIS_WRITE(brdcfg[7], brdcfg7);
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+	board_config_serdes_mux();
+	board_config_usb_mux();
+
+	return 0;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	default:
+		return "150";
+	}
+}
+
+#define NUM_SRDS_BANKS	3
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *srds_regs;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	u8 sw;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < 3; i++) {
+		unsigned int clock = (sw >> (2 * i)) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 3:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		default:
+			printf("Warning: SDREFCLK%u switch setting of '10' is "
+				"unsupported\n", i + 1);
+			break;
+		}
+	}
+
+	srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
+ * 18 means CVDD is 1.8v.
+ */
+static u8 IO_VSEL[] = {
+	33, 33, 33, 25, 25, 25, 18, 18, 18,
+	33, 33, 33, 25, 25, 25, 18, 18, 18,
+	33, 33, 33, 25, 25, 25, 18, 18, 18,
+	33, 33, 33, 33, 33
+};
+
+#define IO_VSEL_MASK	0x1f
+
+/*
+ * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
+ * then set status of  spi flash nodes to 'disabled' according to CVDD.
+ * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
+ * flash2, CVDD '18' will select spi flash3.
+ */
+void fdt_fixup_board_spi(void *blob)
+{
+	u8 sw5 = QIXIS_READ(dutcfg[3]);
+
+	switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
+	/* 3.3v */
+	case 33:
+		do_fixup_by_compat(blob, "atmel,at45db081d", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		break;
+	/* 2.5v */
+	case 25:
+		do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		do_fixup_by_compat(blob, "spansion,en25q32", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		break;
+	/* 1.8v */
+	case 18:
+		do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		do_fixup_by_compat(blob, "spansion,en25q32", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		do_fixup_by_compat(blob, "atmel,at45db081d", "status",
+				"disabled", strlen("disabled") + 1, 1);
+		break;
+	}
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_board_spi(blob);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}

board/freescale/p3060qds/p3060qds.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3060QDS_H__
+#define __P3060QDS_H__
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/u-boot.h>
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+
+#endif

board/freescale/p3060qds/p3060qds_qixis.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3060QDS_QIXIS_H__
+#define __P3060QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for P3060QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EC_MODE_MASK		0x0F
+#define BRDCFG4_EC2_MII_EC1_MII	0x00
+#define BRDCFG4_EC2_MII_EC1_USB	0x03
+#define BRDCFG4_EC2_USB_EC1_MII	0x0C
+#define BRDCFG4_EC2_USB_EC1_USB	0x0F
+#define BRDCFG4_EC2_USB_EC1_RGMII	0x0E
+#define BRDCFG4_EC2_RGMII_EC1_USB	0x0B
+#define BRDCFG4_EC2_RGMII_EC1_RGMII	0x0A
+#define BRDCFG4_EMISEL_MASK		0xF0
+
+#define BRDCFG5_ECLKS_MASK		0x80
+#define BRDCFG5_USB1ID_MASK		0x40
+#define BRDCFG5_USB2ID_MASK		0x20
+#define BRDCFG5_GC2MX_MASK		0x0C
+#define BRDCFG5_T15MX_MASK		0x03
+#define BRDCFG5_ECLKS_IEEE1588_CM	0x80
+#define BRDCFG5_USB1ID_CTRL		0x40
+#define BRDCFG5_USB2ID_CTRL		0x20
+
+#define BRDCFG6_SD1MX_A		0x01
+#define BRDCFG6_SD1MX_B		0x00
+#define BRDCFG6_SD2MX_A		0x02
+#define BRDCFG6_SD2MX_B		0x00
+#define BRDCFG6_SD3MX_A		0x04
+#define BRDCFG6_SD3MX_B		0x00
+#define BRDCFG6_SD4MX_A		0x08
+#define BRDCFG6_SD4MX_B		0x00
+
+#define BRDCFG7_JTAGMX_MASK		0xC0
+#define BRDCFG7_IQ1MX_MASK		0x20
+#define BRDCFG7_G1MX_MASK		0x10
+#define BRDCFG7_D1MX_MASK		0x0C
+#define BRDCFG7_I3MX_MASK		0x03
+#define BRDCFG7_JTAGMX_AURORA		0x00
+#define BRDCFG7_JTAGMX_FPGA		0x80
+#define BRDCFG7_JTAGMX_COP_JTAG	0xC0
+#define BRDCFG7_IQ1MX_IRQ_EVT		0x00
+#define BRDCFG7_IQ1MX_USB2		0x20
+#define BRDCFG7_G1MX_USB1		0x00
+#define BRDCFG7_G1MX_TSEC3		0x10
+#define BRDCFG7_D1MX_DMA		0x00
+#define BRDCFG7_D1MX_TSEC3USB		0x04
+#define BRDCFG7_D1MX_HDLC2		0x08
+#define BRDCFG7_I3MX_UART2_I2C34	0x00
+#define BRDCFG7_I3MX_GPIO_EVT		0x01
+#define BRDCFG7_I3MX_USB1		0x02
+#define BRDCFG7_I3MX_TSEC3		0x03
+
+#endif

boards.cfg

@@ -717,6 +717,8 @@ P2020RDB-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freesca
 P2020RDB-PC_36BIT_NAND       powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT,NAND
 P2020RDB-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD
 P2020RDB-PC_36BIT_SPIFLASH   powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH
+P2020COME_SDCARD             powerpc     mpc85xx     p2020come           freescale      -           P2020COME:SDCARD
+P2020COME_SPIFLASH           powerpc     mpc85xx     p2020come           freescale      -           P2020COME:SPIFLASH
 P2041RDB                     powerpc     mpc85xx     p2041rdb            freescale
 P2041RDB_SDCARD              powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SECURE_BOOT         powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:SECURE_BOOT
@@ -726,6 +728,9 @@ P3041DS_NAND		     powerpc     mpc85xx     corenet_ds          freescale      -
 P3041DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P3041DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SECURE_BOOT
 P3041DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+P3060QDS		     powerpc	 mpc85xx     p3060qds		 freescale
+P3060QDS_NAND		     powerpc     mpc85xx     p3060qds		 freescale	-	    P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+P3060QDS_SECURE_BOOT         powerpc     mpc85xx     p3060qds            freescale      -           P3060QDS:SECURE_BOOT
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
 P4080DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P4080DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SECURE_BOOT

doc/README.p3060qds

@@ -0,0 +1,111 @@
+Overview
+=========
+The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
+
+The P3060 Processor combines six e500mc Power Architecture processor
+cores(1.2GHz) with high-performance datapath acceleration
+architecture(DPAA), CoreNet fabric infrastructure, as well as network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and military/aerospace applications.
+
+
+P3060QDS Board Specifications:
+==============================
+Memory subsystem:
+ * 2G Bytes UDIMM DDR3(64bit bus) with ECC on
+ * 128M Bytes NOR flash single-chip memory
+ * 16M Bytes SPI flash
+ * 8K Bytes AT24C64 I2C EEPROM for RCW
+
+Ethernet(Default SERDES 0x19):
+ * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
+ * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
+ * FM1-dTSEC3: connected to SGMII PHY  (Vitesse VSC8234 port1 in slot1)
+ * FM1-dTSEC4: connected to SGMII PHY  (Vitesse VSC8234 port3 in slot1)
+ * FM2-dTSEC1: connected to SGMII PHY  (Vitesse VSC8234 port0 in slot2)
+ * FM2-dTSEC2: connected to SGMII PHY  (Vitesse VSC8234 port2 in slot2)
+ * FM2-dTSEC3: connected to SGMII PHY  (Vitesse VSC8234 port0 in slot1)
+ * FM2-dTSEC4: connected to SGMII PHY  (Vitesse VSC8234 port2 in slot1)
+
+PCIe:
+ * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
+ * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
+
+RapidIO:
+ * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
+ * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
+
+USB:
+ * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
+ * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
+
+I2C:
+ * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
+	     AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
+ * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
+             ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
+ * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
+ * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
+ * I2C1_CH4: PCIe SLOT1
+ * I2C1_CH5: PCIe SLOT2
+ * I2C1_CH6: PCIe SLOT3
+ * I2C1_CH7: PCIe SLOT4
+ * I2C2: NULL
+ * I2C3: NULL
+
+UART:
+ * Supports two UARTs up to 115200 bps for console
+
+
+Boot from NOR flash
+===================
+1. Build image
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
+	make P3060QDS_config
+	make
+
+2. Program image
+	=> tftp 1000000 u-boot.bin
+	=> protect off all
+	=> erase eff80000 efffffff
+	=> cp.b 1000000 eff80000 80000
+
+3. Program RCW
+	=> tftp 1000000 rcw.bin
+	=> protect off all
+	=> erase e8000000 e801ffff
+	=> cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+	=> tftp 1000000 ucode.bin
+	=> protect off all
+	=> erase ef000000 ef0fffff
+	=> cp.b 1000000 ef000000 2000
+
+5. Change DIP-switch
+	RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
+	Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+	dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
+
+Or use the following command:
+	{linux-2.6}/make p3060qds.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+	{linux-2.6}/arch/powerpc/boot/p3060qds.dtb
+
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+	tftp 1000000 uImage
+	tftp 2000000 rootfs.ext2.gz.uboot
+	tftp 3000000 p3060rdb.dtb
+	bootm 1000000 2000000 3000000
+

drivers/block/fsl_sata.c

@@ -197,27 +197,6 @@ int init_sata(int dev)
 	/* Wait the controller offline */
 	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
 
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
-	/*
-	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
-	 * controller is configured in legacy mode instead of the
-	 * expected enterprise mode. software needs to clear bit[28]
-	 * of HControl register to change to enterprise mode from
-	 * legacy mode.
-	 */
-	{
-		u32 svr = get_svr();
-		if (IS_SVR_REV(svr, 1, 0) &&
-		    ((SVR_SOC_VER(svr) == SVR_P1022) ||
-		     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
-		     (SVR_SOC_VER(svr) == SVR_P1013) ||
-		     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
-			out_le32(&reg->hstatus, 0x20000000);
-			out_le32(&reg->hcontrol, 0x00000100);
-		}
-	}
-#endif
-
 	/* Set the command header base address to CHBA register to tell DMA */
 	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
 

drivers/block/fsl_sata.h

@@ -103,6 +103,7 @@ typedef struct fsl_sata_reg {
 */
 #define HCONTROL_ONOFF			0x80000000 /* Online or offline request */
 #define HCONTROL_FORCE_OFFLINE		0x40000000 /* Force offline request */
+#define HCONTROL_ENTERPRISE_EN		0x10000000 /* Enterprise mode enabled */
 #define HCONTROL_HDR_SNOOP		0x00000400 /* Command header snoop */
 #define HCONTROL_PMP_ATTACHED		0x00000200 /* Port multiplier attached */
 

drivers/net/fm/fm.c

@@ -25,11 +25,11 @@
 #include "fm.h"
 #include "../../qe/qe.h"		/* For struct qe_firmware */
 
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 #include <spi_flash.h>
-#elif defined(CONFIG_SYS_QE_FW_IN_MMC)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 #include <mmc.h>
 #endif
 
@@ -363,21 +363,21 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 {
 	int rc;
 	char env_addr[32];
-#if defined(CONFIG_SYS_FMAN_FW_ADDR)
-	void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
-#elif defined(CONFIG_SYS_QE_FW_IN_NAND)
-	size_t fw_length = CONFIG_SYS_FMAN_FW_LENGTH;
-	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
+#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
+	void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
+	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 
-	rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+	rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
 		       &fw_length, (u_char *)addr);
 	if (rc == -EUCLEAN) {
 		printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
-			CONFIG_SYS_QE_FW_IN_NAND, rc);
+			CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
 	}
 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 	struct spi_flash *ucode_flash;
-	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 	int ret = 0;
 
 	ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
@@ -385,17 +385,17 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	if (!ucode_flash)
 		printf("SF: probe for ucode failed\n");
 	else {
-		ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FW_IN_SPIFLASH,
-				CONFIG_SYS_FMAN_FW_LENGTH, addr);
+		ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
+				CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
 		if (ret)
 			printf("SF: read for ucode failed\n");
 		spi_flash_free(ucode_flash);
 	}
-#elif defined(CONFIG_SYS_QE_FW_IN_MMC)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 	int dev = CONFIG_SYS_MMC_ENV_DEV;
-	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
-	u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512;
-	u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512;
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+	u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+	u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
 	struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 
 	if (!mmc)

drivers/qe/qe.c

@@ -170,11 +170,11 @@ void qe_init(uint qe_base)
 	/* Init the QE IMMR base */
 	qe_immr = (qe_map_t *)qe_base;
 
-#ifdef CONFIG_SYS_QE_FW_ADDR
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
 	/*
 	 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
 	 */
-	qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR);
+	qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
 
 	/* enable the microcode in IRAM */
 	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);

include/configs/MPC8569MDS.h

@@ -510,7 +510,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR	0xfff00000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xfff00000
 
 /*
  * BOOTP options

include/configs/P1022DS.h

@@ -345,7 +345,6 @@
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
-#define CONFIG_FSL_SATA_V2
 
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1

include/configs/P1023RDS.h

@@ -526,12 +526,14 @@ extern unsigned long get_clock_freq(void);
 #ifndef CONFIG_NAND
 /* Default address of microcode for the Linux Fman driver */
 /* QE microcode/firmware address */
-#define CONFIG_SYS_FMAN_FW_ADDR		0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEF000000
 #else
-#define CONFIG_SYS_QE_FW_IN_NAND	0x1f00000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x1f00000
 #endif
-#define CONFIG_SYS_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2

include/configs/P2020COME.h

@@ -0,0 +1,576 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* The P2020COME board is only booted via the Freescale On-Chip ROM */
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+
+#define CONFIG_SYS_TEXT_BASE		0xf8f80000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
+#define CONFIG_P2020		1
+#define CONFIG_P2020COME	1
+#define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+#define CONFIG_MP
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (slot 3) */
+
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		1	/* E1000 pci Ethernet card */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+/*
+ * For P2020COME DDRCLK and SYSCLK are from the same oscillator
+ * For DA phase the SYSCLK is 66MHz
+ * For EA phase the SYSCLK is 100MHz
+ */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0)
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch prediction */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+
+
+
+
+
+
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END		(CONFIG_SYS_INIT_L2_ADDR \
+					+ CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+#define CONFIG_SYS_SDRAM_SIZE		2048ULL	/* DDR size on P2020COME */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00ff0000
+
+#define CONFIG_SYS_SPD_BUS_NUM		1
+#define SPD_EEPROM_ADDRESS		0x53
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR3			2G Cacheable
+ * 0x8000_0000	0x9fff_ffff	PCI Express 3 Mem	1G non-cacheable
+ * 0xa000_0000	0xbfff_ffff	PCI Express 2 Mem	1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI Express 1 Mem	1G non-cacheable
+ * 0xffc1_0000	0xffc1_ffff	PCI Express 3 IO	64K non-cacheable
+ * 0xffc2_0000	0xffc2_ffff	PCI Express 2 IO	64K non-cacheable
+ * 0xffc3_0000	0xffc3_ffff	PCI Express 1 IO	64K non-cacheable
+ *
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* There is no NOR Flash on P2020COME */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	CONFIG_SYS_INIT_RAM_ADDR
+/* the assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE   \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* new uImage format support */
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef  CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR2	0x18
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#if defined(CONFIG_PCI)
+
+/* controller 3, Slot 3, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000  /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000  /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000  /* 64k */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE		0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		2
+#define TSEC3_PHY_ADDR		1
+
+#undef CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+	#define CONFIG_ENV_IS_IN_MMC	1
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+	#define CONFIG_ENV_IS_IN_SPI_FLASH
+	#define CONFIG_ENV_SPI_BUS	0
+	#define CONFIG_ENV_SPI_CS	0
+	#define CONFIG_ENV_SPI_MAX_HZ	10000000
+	#define CONFIG_ENV_SPI_MODE	0
+	#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+	#define CONFIG_ENV_SECT_SIZE	0x10000
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC	1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif /* CONFIG_MMC */
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Misc Extra Settings */
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+#define CONFIG_CMD_DHCP			1
+
+#define CONFIG_CMD_DATE			1
+#define CONFIG_RTC_M41T62		1
+#define CONFIG_SYS_RTC_BUS_NUM		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"hwconfig=fsl_ddr:ecc=on\0"					\
+	"bootcmd=run sdboot\0"						\
+	"sdboot=setenv bootargs root=/dev/mmcblk0p2 rw "		\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+		"$othbootargs; mmcinfo; "				\
+		"ext2load mmc 0:2 $loadaddr /boot/$bootfile; "		\
+		"ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; "		\
+		"bootm $loadaddr - $fdtaddr\0"				\
+	"sdfatboot=setenv bootargs root=/dev/ram rw "			\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+		"$othbootargs; mmcinfo; "				\
+		"fatload mmc 0:1 $loadaddr $bootfile; "			\
+		"fatload mmc 0:1 $fdtaddr $fdtfile; "			\
+		"fatload mmc 0:1 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbboot=setenv bootargs root=/dev/sda1 rw "			\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+		"$othbootargs; "					\
+		"usb start; "						\
+		"ext2load usb 0:1 $loadaddr /boot/$bootfile; "		\
+		"ext2load usb 0:1 $fdtaddr /boot/$fdtfile; "		\
+		"bootm $loadaddr - $fdtaddr\0"				\
+	"usbfatboot=setenv bootargs root=/dev/ram rw "			\
+		"console=$consoledev,$baudrate $othbootargs; "		\
+		"usb start; "						\
+		"fatload usb 0:2 $loadaddr $bootfile; "			\
+		"fatload usb 0:2 $fdtaddr $fdtfile; "			\
+		"fatload usb 0:2 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "			\
+		"console=$consoledev,$baudrate $othbootargs; "		\
+		"usb start; "						\
+		"ext2load usb 0:4 $loadaddr $bootfile; "		\
+		"ext2load usb 0:4 $fdtaddr $fdtfile; "			\
+		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"upgradespi=sf probe 0; "					\
+		"setenv startaddr 0; "					\
+		"setenv erasesize a0000; "				\
+		"tftp 1000000 $tftppath/$uboot_spi; "			\
+		"sf erase $startaddr $erasesize; "			\
+		"sf write 1000000 $startaddr $filesize; "		\
+		"sf erase 100000 120000\0"				\
+	"clearspienv=sf probe 0;sf erase 100000 20000\0"		\
+	"othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0"	\
+	"netdev=eth0\0"							\
+	"rootdelaysecond=15\0"						\
+	"uboot_nor=u-boot-nor.bin\0"					\
+	"uboot_spi=u-boot-p2020.spi\0"					\
+	"uboot_sd=u-boot-p2020.bin\0"					\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=rootfs-dev.ext2.img\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=uImage-2.6.32-p2020.dtb\0"				\
+	"tftppath=p2020\0"
+
+#define CONFIG_HDBOOT							\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"usb start;"							\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"			\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $loadaddr $tftppath/$bootfile;"				\
+	"tftp $fdtaddr $tftppath/$fdtfile;"				\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $ramdiskaddr $tftppath/$ramdiskfile;"			\
+	"tftp $loadaddr $tftppath/$bootfile;"				\
+	"tftp $fdtaddr $tftppath/$fdtfile;"				\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif  /* __CONFIG_H */

include/configs/P2041RDB.h

@@ -414,21 +414,25 @@ unsigned long get_board_sys_clk(unsigned long dummy);
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH	0x110000
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  */
-#define CONFIG_SYS_QE_FW_IN_MMC		(512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FW_IN_NAND	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
-#define CONFIG_SYS_FMAN_FW_ADDR		0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEF000000
 #endif
-#define CONFIG_SYS_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
@@ -446,10 +450,9 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #endif	/* CONFIG_PCI */
 
 /* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LIBATA
 
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1

include/configs/P3041DS.h

@@ -32,7 +32,6 @@
 
 #define CONFIG_MMC
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE3
 #define CONFIG_PCIE4
 #define CONFIG_SYS_DPAA_RMAN

include/configs/P3060QDS.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P3060 QDS board configuration file
+ */
+#define CONFIG_P3060QDS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P3060
+#define CONFIG_FSL_QIXIS
+
+#define CONFIG_NAND_FSL_ELBC
+
+#define CONFIG_ICS307_REFCLK_HZ	25000000  /* ICS307 ref clk freq */
+
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_SST
+
+#include "corenet_ds.h"
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
+#define CONFIG_I2C_MUX
+#define CONFIG_I2C_MULTI_BUS

include/configs/P5020DS.h

@@ -32,7 +32,6 @@
 
 #define CONFIG_MMC
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE3
 #define CONFIG_PCIE4
 #define CONFIG_SYS_FSL_RAID_ENGINE

include/configs/corenet_ds.h

@@ -168,7 +168,11 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR3
 
+#ifdef CONFIG_P3060QDS
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#else
 #define CONFIG_SYS_SPD_BUS_NUM	1
+#endif
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
@@ -474,21 +478,25 @@
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH	0x110000
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  */
-#define CONFIG_SYS_QE_FW_IN_MMC		(512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FW_IN_NAND	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
-#define CONFIG_SYS_FMAN_FW_ADDR		0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEF000000
 #endif
-#define CONFIG_SYS_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
@@ -637,7 +645,7 @@
 
 #define CONFIG_BAUDRATE	115200
 
-#if defined(CONFIG_P4080DS)
+#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
 #define __USB_PHY_TYPE	ulpi
 #else
 #define __USB_PHY_TYPE	utmi

include/configs/p1_p2_rdb_pc.h

@@ -677,8 +677,9 @@
 
 #ifdef CONFIG_QE
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR		0xefec0000
-#define CONFIG_SYS_QE_FW_LENGTH		0x10000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #endif /* CONFIG_QE */
 
 #ifdef CONFIG_P1025RDB

include/ddr_spd.h

@@ -325,5 +325,12 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
 #define DDR3_SPD_MODULETYPE_MICRO_DIMM	(0x04)
 #define DDR3_SPD_MODULETYPE_MINI_RDIMM	(0x05)
 #define DDR3_SPD_MODULETYPE_MINI_UDIMM	(0x06)
+#define DDR3_SPD_MODULETYPE_MINI_CDIMM	(0x07)
+#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM	(0x08)
+#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM	(0x09)
+#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM	(0x0A)
+#define DDR3_SPD_MODULETYPE_LRDIMM	(0x0B)
+#define DDR3_SPD_MODULETYPE_16B_SO_DIMM	(0x0C)
+#define DDR3_SPD_MODULETYPE_32B_SO_DIMM	(0x0D)
 
 #endif /* _DDR_SPD_H_ */