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@@ -38,9 +38,9 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
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}
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}
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/* validate if the memory clk is in the range of dimms */
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/* validate if the memory clk is in the range of dimms */
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if (mclk_ps < tCKmin_X_ps) {
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if (mclk_ps < tCKmin_X_ps) {
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- printf("The DIMM max tCKmin is %d ps,"
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- "doesn't support the MCLK cycle %d ps\n",
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- tCKmin_X_ps, mclk_ps);
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+ printf("DDR clock (MCLK cycle %u ps) is faster than "
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+ "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
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+ mclk_ps, tCKmin_X_ps);
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return 1;
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return 1;
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}
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}
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/* determine the acutal cas latency */
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/* determine the acutal cas latency */
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