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+/*
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+ * (C) Copyright 2010
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+ * Texas Instruments, <www.ti.com>
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+ *
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+ * Authors:
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+ * Aneesh V <aneesh@ti.com>
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+ *
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+ * Derived from OMAP3 work by
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ * Syed Mohammed Khasim <x0khasim@ti.com>
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#ifndef _OMAP4_H_
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+#define _OMAP4_H_
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+
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+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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+#include <asm/types.h>
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+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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+
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+/*
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+ * L4 Peripherals - L4 Wakeup and L4 Core now
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+ */
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+#define OMAP44XX_L4_CORE_BASE 0x4A000000
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+#define OMAP44XX_L4_WKUP_BASE 0x4A300000
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+#define OMAP44XX_L4_PER_BASE 0x48000000
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+
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+/* CONTROL */
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+#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
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+
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+/* UART */
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+#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
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+#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
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+#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
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+
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+/* General Purpose Timers */
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+#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
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+#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
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+#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
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+
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+/* Watchdog Timer2 - MPU watchdog */
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+#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
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+
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+/* 32KTIMER */
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+#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
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+
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+/* GPMC */
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+#define GPMC_BASE 0x50000000
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+
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+/*
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+ * Hardware Register Details
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+ */
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+
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+/* Watchdog Timer */
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+#define WD_UNLOCK1 0xAAAA
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+#define WD_UNLOCK2 0x5555
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+
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+/* GP Timer */
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+#define TCLR_ST (0x1 << 0)
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+#define TCLR_AR (0x1 << 1)
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+#define TCLR_PRE (0x1 << 5)
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+
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+/*
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+ * PRCM
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+ */
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+
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+/* PRM */
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+#define PRM_BASE 0x4A306000
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+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
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+
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+#define PRM_RSTCTRL PRM_DEVICE_BASE
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+
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+#ifndef __ASSEMBLY__
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+
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+struct s32ktimer {
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+ unsigned char res[0x10];
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+ unsigned int s32k_cr; /* 0x10 */
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+};
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+
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+#endif /* __ASSEMBLY__ */
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+
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+/*
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+ * Non-secure SRAM Addresses
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+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
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+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
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+ */
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+#define NON_SECURE_SRAM_START 0x40304000
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+#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
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+/* base address for indirect vectors (internal boot mode) */
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+#define SRAM_ROM_VECT_BASE 0x4030D000
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+/* Temporary SRAM stack used while low level init is done */
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+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
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+
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+/*
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+ * OMAP4 real hardware:
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+ * TODO: Change this to the IDCODE in the hw regsiter
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+ */
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+#define CPU_OMAP4430_ES10 1
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+#define CPU_OMAP4430_ES20 2
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+
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+#endif
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