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@@ -30,20 +30,29 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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-#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
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-#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
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+struct kw_sdram_bank {
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+ u32 win_bar;
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+ u32 win_sz;
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+};
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+
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+struct kw_sdram_addr_dec {
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+ struct kw_sdram_bank sdram_bank[4];
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+};
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+
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/*
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/*
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* kw_sdram_bar - reads SDRAM Base Address Register
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* kw_sdram_bar - reads SDRAM Base Address Register
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*/
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*/
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u32 kw_sdram_bar(enum memory_bank bank)
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u32 kw_sdram_bar(enum memory_bank bank)
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{
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{
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+ struct kw_sdram_addr_dec *base =
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+ (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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u32 result = 0;
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u32 result = 0;
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- u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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if ((!enable) || (bank > BANK3))
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return 0;
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return 0;
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- result = readl(KW_REG_CPUCS_WIN_BAR(bank));
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+ result = readl(&base->sdram_bank[bank].win_bar);
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return result;
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return result;
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}
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}
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@@ -52,12 +61,14 @@ u32 kw_sdram_bar(enum memory_bank bank)
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*/
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*/
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u32 kw_sdram_bs(enum memory_bank bank)
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u32 kw_sdram_bs(enum memory_bank bank)
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{
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{
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+ struct kw_sdram_addr_dec *base =
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+ (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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u32 result = 0;
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u32 result = 0;
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- u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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if ((!enable) || (bank > BANK3))
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return 0;
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return 0;
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- result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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+ result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
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result += 0x01000000;
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result += 0x01000000;
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return result;
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return result;
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}
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}
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