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@@ -35,6 +35,7 @@
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#include <vsc7385.h>
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#include <vsc7385.h>
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#include <netdev.h>
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#include <netdev.h>
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#include <rtc.h>
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#include <rtc.h>
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+#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@@ -142,6 +143,30 @@ int board_early_init_r(void)
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{
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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+ unsigned int orig_bus = i2c_get_bus_num();
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+ u8 i2c_data;
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+
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+ i2c_set_bus_num(1);
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+ if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
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+ 1, &i2c_data, sizeof(i2c_data)) == 0) {
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+ if (i2c_data & 0x2)
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+ puts("NOR Flash Bank : Secondary\n");
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+ else
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+ puts("NOR Flash Bank : Primary\n");
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+
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+ if (i2c_data & 0x1) {
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+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
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+ puts("SD/MMC : 8-bit Mode\n");
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+ puts("eSPI : Disabled\n");
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+ } else {
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+ puts("SD/MMC : 4-bit Mode\n");
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+ puts("eSPI : Enabled\n");
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+ }
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+ } else {
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+ puts("Failed reading I2C Chip 0x18 on bus 1\n");
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+ }
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+ i2c_set_bus_num(orig_bus);
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/*
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/*
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* Remap Boot flash region to caching-inhibited
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* Remap Boot flash region to caching-inhibited
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