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@@ -168,7 +168,12 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
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while (length--) {
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/* We transfer 1 byte */
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+#if defined(CONFIG_MX23)
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+ writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
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+ writel(1, &ssp_regs->hw_ssp_ctrl0_set);
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+#elif defined(CONFIG_MX28)
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writel(1, &ssp_regs->hw_ssp_xfer_size);
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+#endif
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if ((flags & SPI_XFER_END) && !length)
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mxs_spi_end_xfer(ssp_regs);
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@@ -226,6 +231,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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int tl;
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int ret = 0;
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+#if defined(CONFIG_MX23)
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+ const int mxs_spi_pio_words = 1;
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+#elif defined(CONFIG_MX28)
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+ const int mxs_spi_pio_words = 4;
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+#endif
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+
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ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
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memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
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@@ -281,7 +292,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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dp->cmd.data |=
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((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
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- (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
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+ (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
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MXS_DMA_DESC_HALT_ON_TERMINATE |
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MXS_DMA_DESC_TERMINATE_FLUSH;
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@@ -298,15 +309,19 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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}
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/*
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- * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
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+ * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
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+ * case of MX28, write only CTRL0 in case of MX23 due
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+ * to the difference in register layout. It is utterly
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* essential that the XFER_SIZE register is written on
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* a per-descriptor basis with the same size as is the
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* descriptor!
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*/
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dp->cmd.pio_words[0] = ctrl0;
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+#ifdef CONFIG_MX28
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dp->cmd.pio_words[1] = 0;
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dp->cmd.pio_words[2] = 0;
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dp->cmd.pio_words[3] = tl;
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+#endif
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mxs_dma_desc_append(dmach, dp);
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