Merge branch 'master' of /home/wd/git/u-boot/custodians

board/atmel/at91cap9adk/at91cap9adk.c

@@ -196,7 +196,7 @@ static void at91cap9_macb_hw_init(void)
 
 	/* Need to reset PHY -> 500ms reset */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
 				     AT91_RSTC_URSTEN);
 
 	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
@@ -204,6 +204,11 @@ static void at91cap9_macb_hw_init(void)
 	/* Wait for end hardware reset */
 	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
+				     AT91_RSTC_URSTEN);
+
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PB22) |
 	       pin_to_mask(AT91_PIN_PB25) |

board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -80,8 +80,8 @@ static void at91sam9260ek_nand_hw_init(void)
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
 	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 	at91_sys_write(AT91_SMC_PULSE(3),
 		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
 		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
@@ -149,7 +149,7 @@ static void at91sam9260ek_macb_hw_init(void)
 
 	/* Need to reset PHY -> 500ms reset */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
 				     AT91_RSTC_URSTEN);
 
 	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
@@ -159,7 +159,7 @@ static void at91sam9260ek_macb_hw_init(void)
 
 	/* Restore NRST value */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     AT91_RSTC_ERSTL | (0x0 << 8) |
+				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
 				     AT91_RSTC_URSTEN);
 
 	/* Re-enable pull-up */

board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -82,13 +82,13 @@ static void at91sam9261ek_nand_hw_init(void)
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
 	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
-		       AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
@@ -97,7 +97,7 @@ static void at91sam9261ek_nand_hw_init(void)
 #else /* CFG_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(1));
+		       AT91_SMC_TDF_(2));
 
 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
 

board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -83,8 +83,8 @@ static void at91sam9263ek_nand_hw_init(void)
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
 	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 	at91_sys_write(AT91_SMC_PULSE(3),
 		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
 		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
@@ -147,7 +147,7 @@ static void at91sam9263ek_macb_hw_init(void)
 
 	/* Need to reset PHY -> 500ms reset */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
 				     AT91_RSTC_URSTEN);
 
 	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
@@ -155,6 +155,11 @@ static void at91sam9263ek_macb_hw_init(void)
 	/* Wait for end hardware reset */
 	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
+				     AT91_RSTC_URSTEN);
+
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PC25),
 	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);

board/atmel/at91sam9rlek/at91sam9rlek.c

@@ -82,13 +82,13 @@ static void at91sam9rlek_nand_hw_init(void)
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
 	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
-		       AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
@@ -97,7 +97,7 @@ static void at91sam9rlek_nand_hw_init(void)
 #else /* CFG_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(1));
+		       AT91_SMC_TDF_(2));
 
 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);