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@@ -123,8 +123,54 @@ static uec_info_t eth4_uec_info = {
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.enet_interface = CFG_UEC4_INTERFACE_MODE,
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.enet_interface = CFG_UEC4_INTERFACE_MODE,
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};
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};
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#endif
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#endif
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+#ifdef CONFIG_UEC_ETH5
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+static uec_info_t eth5_uec_info = {
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+ .uf_info = {
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+ .ucc_num = CFG_UEC5_UCC_NUM,
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+ .rx_clock = CFG_UEC5_RX_CLK,
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+ .tx_clock = CFG_UEC5_TX_CLK,
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+ .eth_type = CFG_UEC5_ETH_TYPE,
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+ },
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+#if (CFG_UEC5_ETH_TYPE == FAST_ETH)
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+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
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+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
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+#else
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+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
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+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
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+#endif
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+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
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+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
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+ .tx_bd_ring_len = 16,
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+ .rx_bd_ring_len = 16,
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+ .phy_address = CFG_UEC5_PHY_ADDR,
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+ .enet_interface = CFG_UEC5_INTERFACE_MODE,
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+};
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+#endif
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+#ifdef CONFIG_UEC_ETH6
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+static uec_info_t eth6_uec_info = {
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+ .uf_info = {
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+ .ucc_num = CFG_UEC6_UCC_NUM,
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+ .rx_clock = CFG_UEC6_RX_CLK,
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+ .tx_clock = CFG_UEC6_TX_CLK,
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+ .eth_type = CFG_UEC6_ETH_TYPE,
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+ },
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+#if (CFG_UEC6_ETH_TYPE == FAST_ETH)
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+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
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+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
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+#else
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+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
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+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
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+#endif
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+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
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+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
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+ .tx_bd_ring_len = 16,
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+ .rx_bd_ring_len = 16,
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+ .phy_address = CFG_UEC6_PHY_ADDR,
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+ .enet_interface = CFG_UEC6_INTERFACE_MODE,
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+};
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+#endif
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-#define MAXCONTROLLERS (4)
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+#define MAXCONTROLLERS (6)
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static struct eth_device *devlist[MAXCONTROLLERS];
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static struct eth_device *devlist[MAXCONTROLLERS];
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