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ARM: implement erratum 716044 workaround

Add common code to enable the workaround for ARM erratum 716044. This
will be enabled for Tegra.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren 12 years ago
parent
commit
c5d4752c05
2 changed files with 7 additions and 0 deletions
  1. 1 0
      README
  2. 6 0
      arch/arm/cpu/armv7/start.S

+ 1 - 0
README

@@ -485,6 +485,7 @@ The following options need to be configured:
 		Thumb2 this flag will result in Thumb2 code generated by
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 		GCC.
 
 
+		CONFIG_ARM_ERRATA_716044
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_751472

+ 6 - 0
arch/arm/cpu/armv7/start.S

@@ -310,6 +310,12 @@ ENTRY(cpu_init_cp15)
 #endif
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 	mcr	p15, 0, r0, c1, c0, 0
 
 
+#ifdef CONFIG_ARM_ERRATA_716044
+	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
+	orr	r0, r0, #1 << 11	@ set bit #11
+	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_742230
 #ifdef CONFIG_ARM_ERRATA_742230
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	orr	r0, r0, #1 << 4		@ set bit #4