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@@ -20,34 +20,25 @@
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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-void mv_phy_88e1116_init(const char *name)
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+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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- u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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- /* command to read PHY dev address */
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- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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- printf("Err..(%s) could not read PHY dev address\n", __func__);
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- return;
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- }
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-
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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-
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- /* reset the phy */
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- miiphy_reset(name, devadr);
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+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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- printf("88E1116 Initialized on %s\n", name);
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+ if (miiphy_reset(name, phyaddr) == 0)
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+ printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
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