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@@ -32,11 +32,18 @@
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*----------------------------------------------------------------------*/
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#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
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#define CONFIG_440EP 1 /* Specific PPC440EP support */
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-
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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+
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+/*
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+ * Please note that, if NAND support is enabled, the 2nd ethernet port
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+ * can't be used because of pin multiplexing. So, if you want to use the
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+ * 2nd ethernet port you have to "undef" the following define.
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+ */
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+#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
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+
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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@@ -58,13 +65,15 @@
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#define CFG_USB_DEVICE 0x50000000
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#define CFG_NVRAM_BASE_ADDR 0x80000000
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-#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
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+#define CFG_BOOT_BASE_ADDR 0xf0000000
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+#define CFG_NAND_ADDR 0x90000000
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+#define CFG_NAND2_ADDR 0x94000000
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in SDRAM)
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*----------------------------------------------------------------------*/
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-#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
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-#define CFG_INIT_RAM_END 0x1000
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+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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+#define CFG_INIT_RAM_END (8 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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@@ -88,7 +97,7 @@
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* The DS1558 code assumes this condition
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*
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*----------------------------------------------------------------------*/
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-#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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+#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
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/*-----------------------------------------------------------------------
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@@ -118,21 +127,80 @@
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#define CFG_FLASH_ADDR1 0x2aa
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#define CFG_FLASH_WORD_SIZE unsigned char
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-#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
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-#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
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+#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
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+#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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-#if 0 /* test-only */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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-#endif
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#endif /* CFG_ENV_IS_IN_FLASH */
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+/*-----------------------------------------------------------------------
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+ * NAND-FLASH related
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+ *----------------------------------------------------------------------*/
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+#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
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+#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
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+#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
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+#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
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+#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
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+#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
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+#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
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+#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
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+#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
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+#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
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+#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
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+#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
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+#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
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+#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
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+#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
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+#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
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+#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
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+#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
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+#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
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+
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+/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
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+#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
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+#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
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+#define NAND0_CMD_READ2 0x50
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+#define NAND0_CMD_READ_ID 0x90
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+#define NAND0_CMD_READ_STATUS 0x70
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+#define NAND0_CMD_RESET 0xFF
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+#define NAND0_CMD_PAGE_PROG 0x80
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+#define NAND0_CMD_PAGE_PROG_TRUE 0x10
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+#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
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+#define NAND0_CMD_BLOCK_ERASE 0x60
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+#define NAND0_CMD_BLOCK_ERASE_END 0xD0
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+
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+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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+#define SECTORSIZE 512
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+
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+#define ADDR_COLUMN 1
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+#define ADDR_PAGE 2
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+#define ADDR_COLUMN_PAGE 3
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+
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+#define NAND_ChipID_UNKNOWN 0x00
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+#define NAND_MAX_FLOORS 1
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+#define NAND_MAX_CHIPS 1
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+
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+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
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+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
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+#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
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+#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
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+#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
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+
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+/* not needed with 440EP NAND controller */
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+#define NAND_CTL_CLRALE(nandptr)
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+#define NAND_CTL_SETALE(nandptr)
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+#define NAND_CTL_CLRCLE(nandptr)
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+#define NAND_CTL_SETCLE(nandptr)
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+#define NAND_DISABLE_CE(nand)
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+#define NAND_ENABLE_CE(nand)
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+
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------------- */
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@@ -206,10 +274,14 @@
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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-#define CONFIG_NET_MULTI 1 /* required for netconsole */
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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+
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+#ifndef CONFIG_BAMBOO_NAND
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+#define CONFIG_NET_MULTI 1 /* required for netconsole */
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#define CONFIG_PHY1_ADDR 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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+#endif /* CONFIG_BAMBOO_NAND */
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+
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#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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@@ -228,8 +300,15 @@
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#define USB_2_0_DEVICE
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#endif /*CONFIG_440EP*/
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+#ifdef CONFIG_BAMBOO_NAND
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+#define _CFG_CMD_NAND CFG_CMD_NAND
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+#else
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+#define _CFG_CMD_NAND 0
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+#endif /* CONFIG_BAMBOO_NAND */
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+
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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+ CFG_CMD_EEPROM | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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@@ -244,6 +323,7 @@
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_USB | \
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+ _CFG_CMD_NAND | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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@@ -253,42 +333,42 @@
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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-#define CFG_MAXARGS 16 /* max number of command args */
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-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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+#define CFG_MAXARGS 16 /* max number of command args */
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+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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-#define CONFIG_LYNXKDI 1 /* support kdi files */
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+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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+#define CONFIG_LYNXKDI 1 /* support kdi files */
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-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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-#define CONFIG_PCI /* include pci support */
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-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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+#define CONFIG_PCI /* include pci support */
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+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
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+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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-#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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@@ -300,7 +380,7 @@
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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-#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
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+#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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Stefan Roese