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@@ -422,9 +422,9 @@ extern int tqm834x_num_flash_banks;
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#define CFG_SICRL SICRL_LDP_A
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/* i-cache and d-cache disabled */
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-#define CFG_HID0_INIT 0x000000000
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-#define CFG_HID0_FINAL CFG_HID0_INIT
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-#define CFG_HID2 0x000000000
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+#define CFG_HID0_INIT 0x000000000
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+#define CFG_HID0_FINAL CFG_HID0_INIT
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+#define CFG_HID2 HID2_HBE
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/* DDR 0 - 512M */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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@@ -437,12 +437,21 @@ extern int tqm834x_num_flash_banks;
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#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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/* PCI */
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-#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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+#ifdef CONFIG_PCI
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+#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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-#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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+#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
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+#else
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+#define CFG_IBAT3L (0)
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+#define CFG_IBAT3U (0)
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+#define CFG_IBAT4L (0)
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+#define CFG_IBAT4U (0)
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+#define CFG_IBAT5L (0)
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+#define CFG_IBAT5U (0)
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+#endif
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/* IMMRBAR */
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#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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