Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master

MAINTAINERS

@@ -462,10 +462,11 @@ Rune Torgersen <runet@innovsys.com>
 
 Peter Tyser <ptyser@xes-inc.com>
 
-	XPEDITE1000	PPC440GX
-	XPEDITE5170	MPC8640
-	XPEDITE5200	MPC8548
-	XPEDITE5370	MPC8572
+	xpedite1000	PPC440GX
+	xpedite5170	MPC8640
+	xpedite5200	MPC8548
+	xpedite5370	MPC8572
+	xpedite5500	P2020
 
 David Updegraff <dave@cray.com>
 

MAKEALL

@@ -554,9 +554,7 @@ LIST_mips_el="			\
 ## i386 Systems
 #########################################################################
 
-LIST_x86="$(boards_by_arch i386)
-	sc520_eNET	\
-"
+LIST_x86="$(boards_by_arch i386)"
 
 #########################################################################
 ## Nios-II Systems
@@ -609,31 +607,11 @@ LIST_blackfin="$(boards_by_arch blackfin)
 ## SH Systems
 #########################################################################
 
-LIST_sh2="		\
-	rsk7203		\
-"
-LIST_sh3="		\
-	mpr2		\
-	ms7720se	\
-"
-
-LIST_sh4="		\
-	ms7750se	\
-	ms7722se	\
-	MigoR		\
-	r7780mp		\
-	r2dplus		\
-	sh7763rdp	\
-	sh7785lcr	\
-	ap325rxa	\
-	espt		\
-"
+LIST_sh2="$(boards_by_cpu sh2)"
+LIST_sh3="$(boards_by_cpu sh3)"
+LIST_sh4="$(boards_by_cpu sh4)"
 
-LIST_sh="		\
-	${LIST_sh2}	\
-	${LIST_sh3}	\
-	${LIST_sh4}	\
-"
+LIST_sh="$(boards_by_arch sh)"
 
 #########################################################################
 ## SPARC Systems

Makefile

@@ -1184,88 +1184,6 @@ bf527-ezkit-v2_config	: unconfig
 	@$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
 		bf527-ezkit blackfin blackfin bf527-ezkit
 
-#========================================================================
-# SH3 (SuperH)
-#========================================================================
-
-#########################################################################
-## sh2 (Renesas SuperH)
-#########################################################################
-rsk7203_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_RSK7203 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh2 rsk7203 renesas
-
-#########################################################################
-## sh3 (Renesas SuperH)
-#########################################################################
-
-mpr2_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MPR2 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh3 mpr2
-
-ms7720se_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh3 ms7720se
-
-#########################################################################
-## sh4 (Renesas SuperH)
-#########################################################################
-
-MigoR_config :       unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 MigoR renesas
-
-ms7750se_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 ms7750se
-
-ms7722se_config :	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 ms7722se
-
-r2dplus_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 r2dplus renesas
-
-r7780mp_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 r7780mp renesas
-
-sh7763rdp_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 sh7763rdp renesas
-
-sh7785lcr_32bit_config \
-sh7785lcr_config  :   unconfig
-	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/renesas/sh7785lcr
-	@echo "#define CONFIG_SH7785LCR 1" > $(obj)include/config.h
-	@if [ "$(findstring 32bit, $@)" ] ; then \
-		echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
-		echo "CONFIG_SYS_TEXT_BASE = 0x8ff80000" > \
-			$(obj)board/renesas/sh7785lcr/config.tmp ; \
-	fi
-	@$(MKCONFIG) -n $@ -a sh7785lcr sh sh4 sh7785lcr renesas
-
-ap325rxa_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 ap325rxa renesas
-
-espt_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 espt
-
 #########################################################################
 #########################################################################
 

arch/arm/cpu/pxa/start.S

@@ -8,6 +8,7 @@
  *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
  *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
  *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *  Copyright (c) 2010	Marek Vasut <marek.vasut@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -94,20 +95,16 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
 /*
  * These are defined in the board-specific linker script.
  */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
 
-.globl _bss_end
-_bss_end:
-	.word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -127,30 +124,6 @@ FIQ_STACK_START:
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 
-.globl _datarel_start
-_datarel_start:
-	.word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
-	.word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
-	.word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
-	.word __datarelro_start
-
-.globl _got_start
-_got_start:
-	.word __got_start
-
-.globl _got_end
-_got_end:
-	.word __got_end
-
 /*
  * the actual reset code
  */
@@ -272,9 +245,8 @@ stack_setup:
 
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
 	cmp	r0, r6
 	beq	clear_bss
 
@@ -288,36 +260,54 @@ copy_loop:
 	ldmfd sp!, {r0-r12}
 
 #ifndef CONFIG_PRELOADER
-	/* fix got entries */
-	ldr	r1, _TEXT_BASE		/* Text base */
-	mov	r0, r7			/* reloc addr */
-	ldr	r2, _got_start		/* addr in Flash */
-	ldr	r3, _got_end		/* addr in Flash */
-	sub	r3, r3, r1
-	add	r3, r3, r0
-	sub	r2, r2, r1
-	add	r2, r2, r0
-
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r4, [r2]
-	sub	r4, r4, r1
-	add	r4, r4, r0
-	str	r4, [r2]
-	add	r2, r2, #4
+	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23		/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2		/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
 #endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start
-	ldr	r1, _bss_end
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
 	ldr	r3, _TEXT_BASE		/* Text base */
 	mov	r4, r7			/* reloc addr */
-	sub	r0, r0, r3
 	add	r0, r0, r4
-	sub	r1, r1, r3
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
@@ -332,24 +322,33 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
  * initialization, now running from RAM.
  */
 #ifdef CONFIG_ONENAND_IPL
-	ldr     pc, _start_oneboot
+	ldr     r0, _start_oneboot_ofs
+	mov	pc, r0
 
-_start_oneboot: .word start_oneboot
+_start_oneboot_ofs
+	: .word start_oneboot
 #else
-	ldr	r0, _TEXT_BASE
-	ldr	r2, _board_init_r
-	sub	r2, r2, r0
-	add	r2, r2, r7	/* position from board_init_r in RAM */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	r0, r0, r1
+	add	lr, r0, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
 	/* jump to it ... */
-	mov	lr, r2
 	mov	pc, lr
 
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+	.word board_init_r - _start
 #endif
 
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 
 /****************************************************************************/
@@ -567,13 +566,7 @@ fiq:
 /*									    */
 /****************************************************************************/
 /* Operating System Timer */
-OSTIMER_BASE:	.word	0x40a00000
-#define OSMR3	0x0C
-#define OSCR	0x10
-#define OWER	0x18
-#define OIER	0x1C
-
-	.align	5
+.align	5
 .globl reset_cpu
 
 	/* FIXME: this code is PXA250 specific. How is this handled on	    */
@@ -583,18 +576,20 @@ reset_cpu:
 
 	/* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 
-	ldr	r0, OSTIMER_BASE
-	ldr	r1, [r0, #OWER]
+	ldr	r0, =OWER
+	ldr	r1, [r0]
 	orr	r1, r1, #0x0001			/* bit0: WME		    */
-	str	r1, [r0, #OWER]
+	str	r1, [r0]
 
 	/* OS timer does only wrap every 1165 seconds, so we have to set    */
 	/* the match register as well.					    */
 
-	ldr	r1, [r0, #OSCR]			/* read OS timer	    */
+	ldr	r0, =OSCR
+	ldr	r1, [r0]			/* read OS timer	    */
 	add	r1, r1, #0x800			/* let OSMR3 match after    */
 	add	r1, r1, #0x800			/* 4096*(1/3.6864MHz)=1ms   */
-	str	r1, [r0, #OSMR3]
+	ldr	r0, =OSMR3
+	str	r1, [r0]
 
 reset_endless:
 

arch/arm/cpu/pxa/u-boot.lds

@@ -41,21 +41,18 @@ SECTIONS
 	. = ALIGN(4);
 	.data : {
 		*(.data)
-	__datarel_start = .;
-		*(.data.rel)
-	__datarelrolocal_start = .;
-		*(.data.rel.ro.local)
-	__datarellocal_start = .;
-		*(.data.rel.local)
-	__datarelro_start = .;
-		*(.data.rel.ro)
 	}
 
-	__got_start = .;
 	. = ALIGN(4);
-	.got : { *(.got) }
+	__rel_dyn_start = .;
+	.rel.dyn : { *(.rel.dyn) }
+	__rel_dyn_end = .;
+
+	__dynsym_start = .;
+	.dynsym : { *(.dynsym) }
+
+	. = ALIGN(4);
 
-	__got_end = .;
 	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }

arch/arm/include/asm/arch-mx5/crm_regs.h

@@ -189,4 +189,15 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
 
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
+
+/* Define the bits in register CCGRx */
+#define MXC_CCM_CCGR_CG_MASK				0x3
+
+#define MXC_CCM_CCGR5_CG5_OFFSET			10
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
+
 #endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */

arch/arm/lib/board.c

@@ -716,6 +716,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #if defined(CONFIG_CMD_I2C)
 	i2c_reloc();
 #endif
+#if defined(CONFIG_CMD_ONENAND)
+	onenand_reloc();
+#endif
 #endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
 
 #ifdef CONFIG_LOGBUFFER

arch/sh/config.mk

@@ -29,6 +29,6 @@ STANDALONE_LOAD_ADDR += -EB
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
-PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
+PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
 
 LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds

arch/sh/lib/bootm.c

@@ -43,6 +43,41 @@ static void hexdump(unsigned char *buf, int len)
 }
 #endif
 
+#define MOUNT_ROOT_RDONLY	0x000
+#define RAMDISK_FLAGS		0x004
+#define ORIG_ROOT_DEV		0x008
+#define LOADER_TYPE			0x00c
+#define INITRD_START		0x010
+#define INITRD_SIZE			0x014
+#define COMMAND_LINE		0x100
+
+#define RD_PROMPT	(1<<15)
+#define RD_DOLOAD	(1<<14)
+#define CMD_ARG_RD_PROMPT	"prompt_ramdisk="
+#define CMD_ARG_RD_DOLOAD	"load_ramdisk="
+
+#ifdef CONFIG_SH_SDRAM_OFFSET
+#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
+#else
+#define GET_INITRD_START(initrd, linux) (initrd - linux)
+#endif
+
+static void set_sh_linux_param(unsigned long param_addr, unsigned long data)
+{
+	*(unsigned long *)(param_addr) = data;
+}
+
+static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base)
+{
+	unsigned long val = 0;
+	char *p = strstr(cmdline, key);
+	if (p) {
+		p += strlen(key);
+		val = simple_strtol(p, NULL, base);
+	}
+	return val;
+}
+
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
 {
 	/* Linux kernel load address */
@@ -51,7 +86,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	unsigned char *param
 		= (unsigned char *)image_get_load(images->legacy_hdr_os);
 	/* Linux kernel command line */
-	char *cmdline = (char *)param + 0x100;
+	char *cmdline = (char *)param + COMMAND_LINE;
 	/* PAGE_SIZE */
 	unsigned long size = images->ep - (unsigned long)param;
 	char *bootargs = getenv("bootargs");
@@ -61,8 +96,37 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 
 	/* Setup parameters */
 	memset(param, 0, size);	/* Clear zero page */
+
+	/* Set commandline */
 	strcpy(cmdline, bootargs);
 
+	sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+	/* Initrd */
+	if (images->rd_start || images->rd_end) {
+		unsigned long ramdisk_flags = 0;
+		int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10);
+		if (val == 1)
+				ramdisk_flags |= RD_PROMPT;
+		else
+				ramdisk_flags &= ~RD_PROMPT;
+					
+		val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+		if (val == 1)
+				ramdisk_flags |= RD_DOLOAD;
+		else
+				ramdisk_flags &= ~RD_DOLOAD;
+
+		set_sh_linux_param((unsigned long)param + MOUNT_ROOT_RDONLY, 0x0001);
+		set_sh_linux_param((unsigned long)param + RAMDISK_FLAGS, ramdisk_flags);
+		set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
+		set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
+		set_sh_linux_param((unsigned long)param + INITRD_START,
+			GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+		set_sh_linux_param((unsigned long)param + INITRD_SIZE,
+			images->rd_end - images->rd_start);
+	}
+
+	/* Boot kernel */
 	kernel();
 	/* does not return */
 

board/a4m072/a4m072.c

@@ -270,8 +270,6 @@ static u8 display_buf[DISPLAY_BUF_SIZE];
 static u8 display_putc_pos;
 static u8 display_out_pos;
 
-static u8 display_dot_enable;
-
 void display_set(int cmd) {
 
 	if (cmd & DISPLAY_CLEAR) {
@@ -281,12 +279,6 @@ void display_set(int cmd) {
 	if (cmd & DISPLAY_HOME) {
 		display_putc_pos = 0;
 	}
-
-	if (cmd & DISPLAY_MARK) {
-		display_dot_enable = 1;
-	} else {
-		display_dot_enable = 0;
-	}
 }
 
 #define SEG_A    (1<<0)
@@ -314,10 +306,12 @@ void display_set(int cmd) {
  * A..Z		index 10..35
  * -		index 36
  * _		index 37
+ * .		index 38
  */
 
 #define SYMBOL_DASH		(36)
 #define SYMBOL_UNDERLINE	(37)
+#define SYMBOL_DOT		(38)
 
 static u8 display_char2seg7_tbl[]=
 {
@@ -337,28 +331,29 @@ static u8 display_char2seg7_tbl[]=
 	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
 	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
 	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* g */
+	0,					/* g - not displayed */
 	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
-	SEG_E | SEG_F,						/* I */
-	SEG_B | SEG_C | SEG_D | SEG_E,				/* J */
-	SEG_A,						/* K - special 1 */
+	SEG_B | SEG_C,						/* I */
+	0,					/* J - not displayed */
+	0,					/* K - not displayed */
 	SEG_D | SEG_E | SEG_F,					/* L */
-	SEG_B,						/* m - special 2 */
-	SEG_C | SEG_E | SEG_G,					/* n */
-	SEG_C | SEG_D | SEG_E | SEG_G,				/* o */
+	0,					/* m - not displayed */
+	0,					/* n - not displayed */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
 	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
-	SEG_A | SEG_B | SEG_C | SEG_F | SEG_G,			/* q */
-	SEG_E | SEG_G,						/* r */
+	0,					/* q - not displayed */
+	0,					/* r - not displayed */
 	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
 	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
 	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
-	SEG_C | SEG_D | SEG_E | SEG_F,				/* V */
-	SEG_C,						/* w - special 3 */
-	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* X */
+	0,					/* V - not displayed */
+	0,					/* w - not displayed */
+	0,					/* X - not displayed */
 	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
-	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* Z */
+	0,					/* Z - not displayed */
 	SEG_G,							/* - */
-	SEG_D							/* _ */
+	SEG_D,							/* _ */
+	SEG_P							/* . */
 };
 
 /* Convert char to the LED segments representation */
@@ -374,23 +369,20 @@ static u8 display_char2seg7(char c)
 		c -= 'A' - 10;
 	else if (c == '-')
 		c = SYMBOL_DASH;
-	else if ((c == '_') || (c == '.'))
+	else if (c == '_')
 		c = SYMBOL_UNDERLINE;
+	else if (c == '.')
+		c = SYMBOL_DOT;
 	else
 		c = ' ';	/* display unsupported symbols as space */
 
 	if (c != ' ')
 		val = display_char2seg7_tbl[(int)c];
 
-	/* Handle DP LED here */
-	if (display_dot_enable) {
-		val |= SEG_P;
-	}
-
 	return val;
 }
 
-static inline int display_putc_nomark(char c)
+int display_putc(char c)
 {
 	if (display_putc_pos >= DISPLAY_BUF_SIZE)
 		return -1;
@@ -403,13 +395,6 @@ static inline int display_putc_nomark(char c)
 	return c;
 }
 
-int display_putc(char c)
-{
-	/* Mark the codes from the "display" command with the DP LED */
-	display_set(DISPLAY_MARK);
-	return display_putc_nomark(c);
-}
-
 /*
  * Flush current symbol to the LED display hardware
  */
@@ -493,9 +478,8 @@ void show_boot_progress(int status)
 	if (a4m072_status2code(status, buf) < 0)
 		return;
 
-	display_set(0);	/* Clear DP Led */
-	display_putc_nomark(buf[0]);
-	display_putc_nomark(buf[1]);
+	display_putc(buf[0]);
+	display_putc(buf[1]);
 	display_set(DISPLAY_HOME);
 	display_out_pos = 0;	/* reset output position */
 

board/cerf250/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= cerf250.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/cerf250/cerf250.c

@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of cerf PXA Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET

board/cerf250/config.mk

@@ -1,5 +0,0 @@
-#
-# Cerf board with PXA250 cpu
-#
-#
-CONFIG_SYS_TEXT_BASE = 0xa3080000

board/cerf250/lowlevel_init.S

@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr	r0, =GPSR0
-	ldr	r1, =CONFIG_SYS_GPSR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPSR1
-	ldr	r1, =CONFIG_SYS_GPSR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPSR2
-	ldr	r1, =CONFIG_SYS_GPSR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR0
-	ldr	r1, =CONFIG_SYS_GPCR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR1
-	ldr	r1, =CONFIG_SYS_GPCR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR2
-	ldr	r1, =CONFIG_SYS_GPCR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR0
-	ldr	r1, =CONFIG_SYS_GPDR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR1
-	ldr	r1, =CONFIG_SYS_GPDR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR2
-	ldr	r1, =CONFIG_SYS_GPDR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR0_L
-	ldr	r1, =CONFIG_SYS_GAFR0_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR0_U
-	ldr	r1, =CONFIG_SYS_GAFR0_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR1_L
-	ldr	r1, =CONFIG_SYS_GAFR1_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR1_U
-	ldr	r1, =CONFIG_SYS_GAFR1_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR2_L
-	ldr	r1, =CONFIG_SYS_GAFR2_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR2_U
-	ldr	r1, =CONFIG_SYS_GAFR2_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =PSSR			/* enable GPIO pins */
-	ldr	r1, =CONFIG_SYS_PSSR_VAL
-	str	r1, [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
-						/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-
-	ldr	r1, =MEMC_BASE			/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC0_VAL
-	str	r2, [r1, #MSC0_OFFSET]
-	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC1_VAL
-	str	r2, [r1, #MSC1_OFFSET]
-	ldr	r2, [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC2_VAL
-	str	r2, [r1, #MSC2_OFFSET]
-	ldr	r2, [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr	r2, =CONFIG_SYS_MECR_VAL
-	str	r2, [r1, #MECR_OFFSET]
-	ldr	r2, [r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr	r2, =CONFIG_SYS_MCMEM0_VAL
-	str	r2, [r1, #MCMEM0_OFFSET]
-	ldr	r2, [r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr	r2, =CONFIG_SYS_MCMEM1_VAL
-	str	r2, [r1, #MCMEM1_OFFSET]
-	ldr	r2, [r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr	r2, =CONFIG_SYS_MCATT0_VAL
-	str	r2, [r1, #MCATT0_OFFSET]
-	ldr	r2, [r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr	r2, =CONFIG_SYS_MCATT1_VAL
-	str	r2, [r1, #MCATT1_OFFSET]
-	ldr	r2, [r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr	r2, =CONFIG_SYS_MCIO0_VAL
-	str	r2, [r1, #MCIO0_OFFSET]
-	ldr	r2, [r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr	r2, =CONFIG_SYS_MCIO1_VAL
-	str	r2, [r1, #MCIO1_OFFSET]
-	ldr	r2, [r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field, set SDRAM clocks free running */
-
-	ldr	r3, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =0xFFF
-	and	r3, r3,  r2
-
-	ldr	r0, [r1, #MDREFR_OFFSET]
-	bic	r0, r0, r2
-	bic	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
-	orr	r0, r0, r3
-
-	str	r0, [r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
-					MDREFR_K2RUN |MDREFR_K2DB2)
-	and	r4, r4, r2
-	bic	r0, r0, r2
-	orr	r0, r0, r4
-
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r0, r0, #(MDREFR_SLFRSH)
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
-
-	ldr     r4, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
-			MDREFR_K1FREE | MDREFR_K2FREE)
-	and	r4, r4, r2
-	orr	r0, r0, r4
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
-	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4, [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
-						/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3, =CONFIG_SYS_DRAM_BASE
-.rept 8
-	str	r2, [r3]
-.endr
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3, [r1, #MDCNFG_OFFSET]
-	orr	r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2, =CONFIG_SYS_MDMRS_VAL
-	str     r2, [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2, =ICLR
-	str     r1, [r2]
-
-	ldr     r2, =ICMR	/* mask all interrupts at the controller    */
-	str     r1, [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1, =CKEN
-	mov     r2, #0
-	str     r2, [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1, =CCCR
-	str     r2, [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1, =OSCC
-	mov     r2, #OSCC_OON
-	str     r2, [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-	ldr     r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR /* enable no sources */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov     pc, lr

board/colibri_pxa270/Makefile

@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= colibri_pxa270.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/colibri_pxa270/colibri_pxa270.c

@@ -42,8 +42,9 @@ struct serial_device *default_serial_console (void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of vpac270 */
 	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
@@ -54,13 +55,18 @@ int board_init (void)
 	return 0;
 }
 
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
 #ifdef	CONFIG_CMD_USB

board/colibri_pxa270/config.mk

@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000

board/colibri_pxa270/lowlevel_init.S

@@ -1,36 +0,0 @@
-/*
- * Toradex Colibri PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr

board/cradle/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= cradle.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/cradle/config.mk

@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa0f80000
-#CONFIG_SYS_TEXT_BASE = 0

board/cradle/cradle.c

@@ -185,6 +185,10 @@ int
 board_init (void)
 /**********************************************************/
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	led_code (0xf, YELLOW);
 
 	/* arch number of HHP Cradle */
@@ -206,24 +210,18 @@ board_init (void)
 	return 1;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
-
-	return (PHYS_SDRAM_1_SIZE +
-		PHYS_SDRAM_2_SIZE +
-		PHYS_SDRAM_3_SIZE +
-		PHYS_SDRAM_4_SIZE );
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
 #ifdef CONFIG_CMD_NET

board/cradle/lowlevel_init.S

@@ -1,515 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-   .macro SET_LED val
-   ldr   r6, =GPCR2
-   ldr   r7, =0
-   str   r7, [r6]
-   ldr   r6, =GPSR2
-   ldr   r7, =\val
-   str   r7, [r6]
-   .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-    /* Set up GPIO pins first */
-
-   ldr      r0,   =GPSR0
-   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPSR1
-   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPSR2
-   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR0
-   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR1
-   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR2
-   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER0
-   ldr      r1,   =CONFIG_SYS_GRER0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER1
-   ldr      r1,   =CONFIG_SYS_GRER1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER2
-   ldr      r1,   =CONFIG_SYS_GRER2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER0
-   ldr      r1,   =CONFIG_SYS_GFER0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER1
-   ldr      r1,   =CONFIG_SYS_GFER1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER2
-   ldr      r1,   =CONFIG_SYS_GFER2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR0_L
-   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR0_U
-   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR1_L
-   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR1_U
-   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR2_L
-   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR2_U
-   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
-   str      r1,   [r0]
-
-   /* enable GPIO pins */
-   ldr      r0,   =PSSR
-   ldr      r1,   =CONFIG_SYS_PSSR_VAL
-   str      r1,   [r0]
-
-   SET_LED 1
-
-   ldr    r3, =MSC1             /* low - bank 2 Lubbock Registers / SRAM */
-   ldr    r2, =CONFIG_SYS_MSC1_VAL     /* high - bank 3 Ethernet Controller */
-   str    r2, [r3]              /* need to set MSC1 before trying to write to the HEX LEDs */
-   ldr    r2, [r3]              /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
-    Initlialize Memory Controller
-
-    See PXA250 Operating System Developer's Guide
-
-    pause for 200 uSecs- allow internal clocks to settle
-    *Note: only need this if hard reset... doing it anyway for now
-*/
-
-    @ Step 1
-   @ ---- Wait 200 usec
-   ldr r3, =OSCR       @ reset the OS Timer Count to zero
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300         @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-   SET_LED 2
-
-mem_init:
-	@ get memory controller base address
-	ldr     r1,  =MEMC_BASE
-
-
-@****************************************************************************
-@  Step 2
-@
-
-   @ Step 2a
-   @ write msc0, read back to ensure data latches
-   @
-   ldr     r2,   =CONFIG_SYS_MSC0_VAL
-   str     r2,   [r1, #MSC0_OFFSET]
-   ldr     r2,   [r1, #MSC0_OFFSET]
-
-   @ write msc1
-   ldr     r2,  =CONFIG_SYS_MSC1_VAL
-   str     r2,  [r1, #MSC1_OFFSET]
-   ldr     r2,  [r1, #MSC1_OFFSET]
-
-   @ write msc2
-   ldr     r2,  =CONFIG_SYS_MSC2_VAL
-   str     r2,  [r1, #MSC2_OFFSET]
-   ldr     r2,  [r1, #MSC2_OFFSET]
-
-   @ Step 2b
-   @ write mecr
-   ldr     r2,  =CONFIG_SYS_MECR_VAL
-   str     r2,  [r1, #MECR_OFFSET]
-
-   @ write mcmem0
-   ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-   str     r2,  [r1, #MCMEM0_OFFSET]
-
-   @ write mcmem1
-   ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-   str     r2,  [r1, #MCMEM1_OFFSET]
-
-   @ write mcatt0
-   ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-   str     r2,  [r1, #MCATT0_OFFSET]
-
-   @ write mcatt1
-   ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-   str     r2,  [r1, #MCATT1_OFFSET]
-
-   @ write mcio0
-   ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-   str     r2,  [r1, #MCIO0_OFFSET]
-
-   @ write mcio1
-   ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-   str     r2,  [r1, #MCIO1_OFFSET]
-
-   /*SET_LED 3 */
-
-   @ Step 2c
-   @ fly-by-dma is defeatured on this part
-   @ write flycnfg
-   @ldr     r2,  =CONFIG_SYS_FLYCNFG_VAL
-   @str     r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-   @ Step 2d
-   @ get the mdrefr settings
-   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
-
-   @ extract DRI field (we need a valid DRI field)
-   @
-   ldr     r2,  =0xFFF
-
-   @ valid DRI field in r3
-   @
-   and     r3,  r3,  r2
-
-   @ get the reset state of MDREFR
-   @
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ clear the DRI field
-   @
-   bic     r4,  r4,  r2
-
-   @ insert the valid DRI field loaded above
-   @
-   orr     r4,  r4,  r3
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ *Note: preserve the mdrefr value in r4 *
-
-   /*SET_LED 4 */
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-   mov   pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-   @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-   @ clear the free-running clock bits
-   @ (clear K0Free, K1Free, K2Free
-   @
-   bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-   @ set K0RUN for CPLD clock
-   @
-   orr   r4,  r4,  #0x00002000
-
-   @ set K1RUN if bank 0 installed
-   @
-   orr   r4,  r4,  #0x00010000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ deassert SLFRSH
-   @
-   bic     r4,  r4,  #0x00400000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ assert E1PIN
-   @
-   orr     r4,  r4,  #0x00008000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-   nop
-   nop
-#else
-   @ Step 2d
-   @ get the mdrefr settings
-   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @  Step 4
-
-   @ set K0RUN for CPLD clock
-   @
-   orr   r4,  r4,  #0x00002000
-
-   @ set K1RUN for bank 0
-   @
-   orr   r4,  r4,  #0x00010000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ deassert SLFRSH
-   @
-   bic     r4,  r4,  #0x00400000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ assert E1PIN
-   @
-   orr     r4,  r4,  #0x00008000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-   nop
-   nop
-#endif
-
-   @ Step 4d
-   @ fetch platform value of mdcnfg
-   @
-   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-   @ disable all sdram banks
-   @
-   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-   @ program banks 0/1 for bus width
-   @
-   bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
-
-   @ write initial value of mdcnfg, w/o enabling sdram banks
-   @
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-   @ Step 4e
-   @ pause for 200 uSecs
-   @
-   ldr r3, =OSCR       @ reset the OS Timer Count to zero
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-   /*SET_LED 5 */
-
-   /* Why is this here??? */
-   mov    r0, #0x78                @turn everything off
-   mcr    p15, 0, r0, c1, c0, 0      @(caches off, MMU off, etc.)
-
-   @ Step 4f
-   @ Access memory *not yet enabled* for CBR refresh cycles (8)
-   @ - CBR is generated for all banks
-
-   ldr     r2, =CONFIG_SYS_DRAM_BASE
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-
-   @ Step 4g
-   @get memory controller base address
-   @
-   ldr     r1,  =MEMC_BASE
-
-   @fetch current mdcnfg value
-   @
-   ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-   @enable sdram bank 0 if installed (must do for any populated bank)
-   @
-   orr     r3,  r3,  #MDCNFG_DE0
-
-   @write back mdcnfg, enabling the sdram bank(s)
-   @
-   str     r3,  [r1, #MDCNFG_OFFSET]
-
-   @ Step 4h
-   @ write mdmrs
-   @
-   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-   str     r2,  [r1, #MDMRS_OFFSET]
-
-   @ Done Memory Init
-
-   /*SET_LED 6 */
-
-   @********************************************************************
-   @ Disable (mask) all interrupts at the interrupt controller
-   @
-
-   @ clear the interrupt level register (use IRQ, not FIQ)
-   @
-   mov     r1, #0
-   ldr     r2,  =ICLR
-   str     r1,  [r2]
-
-   @ Set interrupt mask register
-   @
-   ldr     r1,  =CONFIG_SYS_ICMR_VAL
-   ldr     r2,  =ICMR
-   str     r1,  [r2]
-
-   @ ********************************************************************
-   @ Disable the peripheral clocks, and set the core clock
-   @
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-   ldr     r1,  =CKEN
-   mov     r2,  #0
-   str     r2,  [r1]
-
-   @ set core clocks
-   @
-   ldr     r2,  =CONFIG_SYS_CCCR_VAL
-   ldr     r1,  =CCCR
-   str     r2,  [r1]
-
-#ifdef ENABLE32KHZ
-   @ enable the 32Khz oscillator for RTC and PowerManager
-   @
-   ldr     r1,  =OSCC
-   mov     r2,  #OSCC_OON
-   str     r2,  [r1]
-
-   @ NOTE:  spin here until OSCC.OOK get set,
-   @        meaning the PLL has settled.
-   @
-60:
-   ldr     r2, [r1]
-   ands    r2, r2, #1
-   beq     60b
-#endif
-
-	@ Turn on needed clocks
-	@
-   ldr     r1,  =CKEN
-   ldr     r2,  =CONFIG_SYS_CKEN_VAL
-   str     r2,  [r1]
-
-   /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-   /*Disable software and data breakpoints */
-   mov   r0,#0
-   mcr   p15,0,r0,c14,c8,0  /* ibcr0 */
-   mcr   p15,0,r0,c14,c9,0  /* ibcr1 */
-   mcr   p15,0,r0,c14,c4,0  /* dbcon */
-
-   /*Enable all debug functionality */
-   mov   r0,#0x80000000
-   mcr   p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-   /*SET_LED 8 */
-
-   mov   pc, r10
-
-@ End lowlevel_init

board/csb226/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= csb226.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/csb226/config.mk

@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000

board/csb226/csb226.c

@@ -69,8 +69,9 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of CSB226 board */
 	gd->bd->bi_arch_number = MACH_TYPE_CSB226;
@@ -82,21 +83,20 @@ int board_init (void)
 }
 
 
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
-
 /**
  * csb226_set_led: - switch LEDs on or off
  *

board/csb226/lowlevel_init.S

@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
-/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
-/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/*	ldr	r1,	=LED_BLANK */
-/*	mov	r0,	#0xFF */
-/*	str	r0,	[r1]		/  turn on hex leds */
-/* */
-/*loop: */
-/* */
-/*   ldr	r0, =0xB0070001 */
-/*   ldr	r1, =_LED */
-/*   str	r0, [r1]		/  hex display */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
-	adr	r3, mem_init		/* r0 <- current position of code   */
-	ldr	r2, =mem_init
-	cmp	r3, r2			/* skip init if in place            */
-	beq	initirqs
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	ldr	r2,	=0xFFF
-	and	r3,	r3, r2
-	ldr	r4,	=0x03ca4000
-	orr	r4,	r4,  r3
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,	[r1, #MDREFR_OFFSET]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* Step 4a: assert MDREFR:K?RUN and configure                       */
-	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
-
-	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4, #(MDREFR_SLFRSH)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
-
-	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	/*          There should 9 writes, since the first write doesn't    */
-	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
-	/*          PXA210 Processors Specification Update,                 */
-	/*          Jan 2003, Errata #116, page 30.                         */
-
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr	r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str	r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-/*
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-*/
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size                                                  */
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR			/* enable no sources        */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#ifndef DEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr

board/delta/Makefile

@@ -1,52 +0,0 @@
-
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= delta.o nand.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

board/delta/config.mk

@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x83008000

board/delta/delta.c

@@ -1,378 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <da9030.h>
-#include <malloc.h>
-#include <command.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static void init_DA9030(void);
-static void keys_init(void);
-static void get_pressed_keys(uchar *s);
-static uchar *key_match(uchar *kbd_data);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
-
-	/* arch number of Lubbock-Board mk@tbd: fix this! */
-	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef DELTA_CHECK_KEYBD
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	char *str;
-	int i;
-#endif /* DELTA_CHECK_KEYBD */
-
-	setenv("stdout", "serial");
-	setenv("stderr", "serial");
-
-#ifdef DELTA_CHECK_KEYBD
-	keys_init();
-
-	memset(kbd_data, '\0', KEYBD_DATALEN);
-
-	/* check for pressed keys and setup keybd_env */
-	get_pressed_keys(kbd_data);
-
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-	}
-	setenv ("keybd", keybd_env);
-
-	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
-
-# ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	setenv ("preboot", str);	/* set or delete definition */
-# endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-#endif /* DELTA_CHECK_KEYBD */
-
-	init_DA9030();
-	return 0;
-}
-
-/*
- * Magic Key Handling, mainly copied from board/lwmon/lwmon.c
- */
-#ifdef DELTA_CHECK_KEYBD
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-/*
- * Get pressed keys
- * s is a buffer of size KEYBD_DATALEN-1
- */
-static void get_pressed_keys(uchar *s)
-{
-	unsigned long val;
-	val = readl(GPLR3);
-
-	if(val & (1<<31))
-		*s++ = KEYBD_KP_DKIN0;
-	if(val & (1<<18))
-		*s++ = KEYBD_KP_DKIN1;
-	if(val & (1<<29))
-		*s++ = KEYBD_KP_DKIN2;
-	if(val & (1<<22))
-		*s++ = KEYBD_KP_DKIN5;
-}
-
-static void keys_init()
-{
-	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
-	udelay(100);
-
-	/* Configure GPIOs */
-	writel(0xa840, GPIO127);	/* KP_DKIN0 */
-	writel(0xa840, GPIO114);	/* KP_DKIN1 */
-	writel(0xa840, GPIO125);	/* KP_DKIN2 */
-	writel(0xa840, GPIO118);	/* KP_DKIN5 */
-
-	/* Configure GPIOs as inputs */
-	writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
-	writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
-
-	udelay(100);
-}
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
-	/* uchar compare[KEYBD_DATALEN-1]; */
-	uchar compare[KEYBD_DATALEN];
-	char *nxt;
-	int i;
-
-	/* Don't include modifier byte */
-	/* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
-	memcpy (compare, kbd_data, KEYBD_DATALEN);
-
-	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
-		uchar c;
-		int k;
-
-		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
-		if (str == (uchar *)nxt) {	/* invalid character */
-			break;
-		}
-
-		/*
-		 * Check if this key matches the input.
-		 * Set matches to zero, so they match only once
-		 * and we can find duplicates or extra keys
-		 */
-		for (k = 0; k < sizeof(compare); ++k) {
-			if (compare[k] == '\0')	/* only non-zero entries */
-				continue;
-			if (c == compare[k]) {	/* found matching key */
-				compare[k] = '\0';
-				break;
-			}
-		}
-		if (k == sizeof(compare)) {
-			return -1;		/* unmatched key */
-		}
-	}
-
-	/*
-	 * A full match leaves no keys in the `compare' array,
-	 */
-	for (i = 0; i < sizeof(compare); ++i) {
-		if (compare[i])
-		{
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-
-static uchar *key_match (uchar *kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-#if 0
-		printf ("### Check magic \"%s\"\n", magic);
-#endif
-		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
-			char cmd_name[sizeof (kbd_command_prefix) + 1];
-			char *cmd;
-
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
-			cmd = getenv (cmd_name);
-#if 0
-			printf ("### Set PREBOOT to $(%s): \"%s\"\n",
-				cmd_name, cmd ? cmd : "<<NULL>>");
-#endif
-			*kbd_data = *suffix;
-			return ((uchar *)cmd);
-		}
-	}
-#if 0
-	printf ("### Delete PREBOOT\n");
-#endif
-	*kbd_data = '\0';
-	return (NULL);
-}
-
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	int i;
-
-	/* Read keys */
-	get_pressed_keys(kbd_data);
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-		printf (" %02x", kbd_data[i]);
-	}
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	   kbd,	1,	1,	do_kbd,
-	   "read keyboard status",
-	   ""
-);
-
-#endif /* DELTA_CHECK_KEYBD */
-
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
-}
-
-void i2c_init_board()
-{
-	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-
-	/* setup I2C GPIO's */
-	writel(0x801, GPIO32);		/* SCL = Alt. Fkt. 1 */
-	writel(0x801, GPIO33);		/* SDA = Alt. Fkt. 1 */
-}
-
-/* initialize the DA9030 Power Controller */
-static void init_DA9030()
-{
-	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-
-	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
-	udelay(100);
-
-	/* Rising Edge on EXTON to reset DA9030 */
-	writel(0x8800, GPIO17);	/* configure GPIO17, no pullup, -down */
-	writel(readl(GPDR0) | (1<<17), GPDR0);	/* GPIO17 is output */
-	writel((1<<17), GSDR0);
-	writel((1<<17), GPCR0);	/* drive GPIO17 low */
-	writel((1<<17), GPSR0);	/* drive GPIO17 high */
-
-#if CONFIG_SYS_DA9030_EXTON_DELAY
-	udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY);	/* wait for DA9030 */
-#endif
-	writel((1<<17), GPCR0);	/* drive GPIO17 low */
-
-	/* reset the watchdog and go active (0xec) */
-	val = (SYS_CONTROL_A_HWRES_ENABLE |
-	       (0x6<<4) |
-	       SYS_CONTROL_A_WDOG_ACTION |
-	       SYS_CONTROL_A_WATCHDOG);
-	if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
-		printf("Error accessing DA9030 via i2c.\n");
-		return;
-	}
-
-	val = 0x80;
-	if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
-		printf("Error accessing DA9030 via i2c.\n");
-		return;
-	}
-
-	i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
-	i2c_reg_write(addr, LDO2_3, 0xd1);	/* LDO2 =1,9V, LDO3=3,1V */
-	i2c_reg_write(addr, LDO4_5, 0xcc);	/* LDO2 =1,9V, LDO3=3,1V */
-	i2c_reg_write(addr, LDO6_SIMCP, 0x3e);	/* LDO6=3,2V, SIMCP = 5V support */
-	i2c_reg_write(addr, LDO7_8, 0xc9);	/* LDO7=2,7V, LDO8=3,0V */
-	i2c_reg_write(addr, LDO9_12, 0xec);	/* LDO9=3,0V, LDO12=3,2V */
-	i2c_reg_write(addr, BUCK, 0x0c);	/* Buck=1.2V */
-	i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
-	i2c_reg_write(addr, LDO_10_11, 0xcc);	/* LDO10=3.0V  LDO11=3.0V */
-	i2c_reg_write(addr, LDO_15, 0xae);	/* LDO15=1.8V, dislock first 3bit */
-	i2c_reg_write(addr, LDO_14_16, 0x05);	/* LDO14=2.8V, LDO16=NB */
-	i2c_reg_write(addr, LDO_18_19, 0x9c);	/* LDO18=3.0V, LDO19=2.7V */
-	i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
-	i2c_reg_write(addr, BUCK2_DVC1, 0x9a);	/* Buck2=1.5V plus Update support of 520 MHz */
-	i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
-	i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
-	i2c_reg_write(addr, USBPUMP, 0xc1);	/* start pump, ignore HW signals */
-
-	val = i2c_reg_read(addr, STATUS);
-	if(val & STATUS_CHDET)
-		printf("Charger detected, turning on LED.\n");
-	else {
-		printf("No charger detetected.\n");
-		/* undervoltage? print error and power down */
-	}
-}
-
-
-#if 0
-/* reset the DA9030 watchdog */
-void hw_watchdog_reset(void)
-{
-	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-	val = i2c_reg_read(addr, SYS_CONTROL_A);
-	val |= SYS_CONTROL_A_WATCHDOG;
-	i2c_reg_write(addr, SYS_CONTROL_A, val);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif

board/delta/lowlevel_init.S

@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-.macro wait time
-	ldr		r2, =OSCR
-	mov		r3, #0
-	str		r3, [r2]
-0:
-	ldr		r3, [r2]
-	cmp		r3, \time
-	bls		0b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Set up GPIO pins first */
-	mov	 r10, lr
-
-	/*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
-	ldr		r0, =GPIO97
-	ldr		r1, =0x801
-	str		r1, [r0]
-
-	ldr		r0, =GPIO98
-	ldr		r1, =0x801
-	str		r1, [r0]
-
-	/* tebrandt - ASCR, clear the RDH bit */
-	ldr		r0, =ASCR
-	ldr		r1, [r0]
-	bic		r1, r1, #0x80000000
-	str		r1, [r0]
-
-mem_init:
-	/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
-	ldr		r0, =ACCR
-	ldr		r1, [r0]
-	orr		r1, r1, #0x3000
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
-	ldr		r0, =MDCNFG
-	ldr		r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
-	/* ldr		r1, =0x80000403 */
-	str		r1, [r0]
-	ldr		r1, [r0]	/* delay until written */
-
-	/* 3. wait nop power up waiting period (200ms)
-	 * optimization: Steps 4+6 can be done during this
-	 */
-	wait #0x300
-
-	/* 4. Perform an initial Rcomp-calibration cycle */
-	ldr		r0, =RCOMP
-	ldr		r1, =0x80000000
-	str		r1, [r0]
-	ldr		r1, [r0]	/* delay until written */
-	/* missing: program for automatic rcomp evaluation cycles */
-
-	/* 5. DDR DRAM strobe delay calibration */
-	ldr		r0, =DDR_HCAL
-	ldr		r1, =0x88000007
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]	/* delay until written */
-
-	/* Set MDMRS */
-	ldr		r0, =MDMRS
-	ldr		r1, =0x60000033
-	str		r1, [r0]
-	wait	#300
-
-	/* Configure MDREFR */
-	ldr		r0, =MDREFR
-	ldr		r1, =0x00000006
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Enable the dynamic memory controller */
-	ldr		r0, =MDCNFG
-	ldr		r1, [r0]
-	orr		r1, r1, #MDCNFG_DMCEN
-	str		r1, [r0]
-
-#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
-	/* scrub/init SDRAM if enabled/present */
-	ldr	r8, =CONFIG_SYS_DRAM_BASE	/* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
-	ldr	r9, =CONFIG_SYS_DRAM_SIZE	/* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
-	mov	r0, #0			/* scrub with 0x0000:0000 */
-	mov	r1, #0
-	mov	r2, #0
-	mov	r3, #0
-	mov	r4, #0
-	mov	r5, #0
-	mov	r6, #0
-	mov	r7, #0
-10:	/* fastScrubLoop */
-	subs	r9, r9, #32	/* 8 words/line */
-	stmia	r8!, {r0-r7}
-	beq	15f
-	b	10b
-#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
-
-15:
-	/* Mask all interrupts */
-	mov	r1, #0
-	mcr	p6, 0, r1, c1, c0, 0	@ ICMR
-
-	/* Disable software and data breakpoints */
-	mov	r0, #0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/* Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-endlowlevel_init:
-	mov	pc, lr

board/delta/nand.c

@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_DFC_DEBUG1
-# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG1(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG2
-# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG2(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG3
-# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG3(fmt, args...)
-#endif
-
-/* These really don't belong here, as they are specific to the NAND Model */
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr delta_bbt_descr = {
-	.options = 0,
-	.offs = 0,
-	.len = 2,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout delta_oob = {
-	.eccbytes = 6,
-	.eccpos = {2, 3, 4, 5, 6, 7},
-	.oobfree = { {8, 2}, {12, 4} }
-};
-
-/*
- * not required for Monahans DFC
- */
-static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	return;
-}
-
-#if 0
-/* read device ready pin */
-static int dfc_device_ready(struct mtd_info *mtdinfo)
-{
-	if(NDSR & NDSR_RDY)
-		return 1;
-	else
-		return 0;
-	return 0;
-}
-#endif
-
-/*
- * Write buf to the DFC Controller Data Buffer
- */
-static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	unsigned long bytes_multi = len & 0xfffffffc;
-	unsigned long rest = len & 0x3;
-	unsigned long *long_buf;
-	int i;
-
-	DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
-	if(bytes_multi) {
-		for(i=0; i<bytes_multi; i+=4) {
-			long_buf = (unsigned long*) &buf[i];
-			writel(*long_buf, NDDB);
-		}
-	}
-	if(rest) {
-		printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
-	}
-	return;
-}
-
-
-static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
-{
-	int i=0, j;
-
-	/* we have to be carefull not to overflow the buffer if len is
-	 * not a multiple of 4 */
-	unsigned long bytes_multi = len & 0xfffffffc;
-	unsigned long rest = len & 0x3;
-	unsigned long *long_buf;
-
-	DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
-	/* if there are any, first copy multiple of 4 bytes */
-	if(bytes_multi) {
-		for(i=0; i<bytes_multi; i+=4) {
-			long_buf = (unsigned long*) &buf[i];
-			*long_buf = readl(NDDB);
-		}
-	}
-
-	/* ...then the rest */
-	if(rest) {
-		unsigned long rest_data = NDDB;
-		for(j=0;j<rest; j++)
-			buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
-	}
-
-	return;
-}
-
-/*
- * read a word. Not implemented as not used in NAND code.
- */
-static u16 dfc_read_word(struct mtd_info *mtd)
-{
-	printf("dfc_read_word: UNIMPLEMENTED.\n");
-	return 0;
-}
-
-/* global var, too bad: mk@tbd: move to ->priv pointer */
-static unsigned long read_buf = 0;
-static int bytes_read = -1;
-
-/*
- * read a byte from NDDB Because we can only read 4 bytes from NDDB at
- * a time, we buffer the remaining bytes. The buffer is reset when a
- * new command is sent to the chip.
- *
- * WARNING:
- * This function is currently only used to read status and id
- * bytes. For these commands always 8 bytes need to be read from
- * NDDB. So we read and discard these bytes right now. In case this
- * function is used for anything else in the future, we must check
- * what was the last command issued and read the appropriate amount of
- * bytes respectively.
- */
-static u_char dfc_read_byte(struct mtd_info *mtd)
-{
-	unsigned char byte;
-	unsigned long dummy;
-
-	if(bytes_read < 0) {
-		read_buf = readl(NDDB);
-		dummy = readl(NDDB);
-		bytes_read = 0;
-	}
-	byte = (unsigned char) (read_buf>>(8 * bytes_read++));
-	if(bytes_read >= 4)
-		bytes_read = -1;
-
-	DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
-	return byte;
-}
-
-/* calculate delta between OSCR values start and now  */
-static unsigned long get_delta(unsigned long start)
-{
-	unsigned long cur = readl(OSCR);
-
-	if(cur < start) /* OSCR overflowed */
-		return (cur + (start^0xffffffff));
-	else
-		return (cur - start);
-}
-
-/* delay function, this doesn't belong here */
-static void wait_us(unsigned long us)
-{
-	unsigned long start = readl(OSCR);
-	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
-
-	while (get_delta(start) < us) {
-		/* do nothing */
-	}
-}
-
-static void dfc_clear_nddb(void)
-{
-	writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
-	wait_us(CONFIG_SYS_NAND_OTHER_TO);
-}
-
-/* wait_event with timeout */
-static unsigned long dfc_wait_event(unsigned long event)
-{
-	unsigned long ndsr, timeout, start = readl(OSCR);
-
-	if(!event)
-		return 0xff000000;
-	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
-					* OSCR_CLK_FREQ, 1000);
-	else
-		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
-					* OSCR_CLK_FREQ, 1000);
-
-	while(1) {
-		ndsr = readl(NDSR);
-		if(ndsr & event) {
-			writel(readl(NDSR) | event, NDSR);
-			break;
-		}
-		if(get_delta(start) > timeout) {
-			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
-			return 0xff000000;
-		}
-
-	}
-	return ndsr;
-}
-
-/* we don't always wan't to do this */
-static void dfc_new_cmd(void)
-{
-	int retry = 0;
-	unsigned long status;
-
-	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
-		/* Clear NDSR */
-		writel(0xfff, NDSR);
-
-		/* set NDCR[NDRUN] */
-		if (!(readl(NDCR) & NDCR_ND_RUN))
-			writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
-
-		status = dfc_wait_event(NDSR_WRCMDREQ);
-
-		if(status & NDSR_WRCMDREQ)
-			return;
-
-		DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
-		dfc_clear_nddb();
-	}
-	DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
-}
-
-/* this function is called after Programm and Erase Operations to
- * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
-{
-	unsigned long ndsr=0, event=0;
-	int state = this->state;
-
-	if(state == FL_WRITING) {
-		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
-	} else if(state == FL_ERASING) {
-		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
-	}
-
-	ndsr = dfc_wait_event(event);
-
-	if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
-		return(0x1); /* Status Read error */
-	return 0;
-}
-
-/* cmdfunc send commands to the DFC */
-static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
-			int column, int page_addr)
-{
-	/* register struct nand_chip *this = mtd->priv; */
-	unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
-
-	/* clear the ugly byte read buffer */
-	bytes_read = -1;
-	read_buf = 0;
-
-	switch (command) {
-	case NAND_CMD_READ0:
-		DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		dfc_new_cmd();
-		ndcb0 = (NAND_CMD_READ0 | (4<<16));
-		column >>= 1; /* adjust for 16 bit bus */
-		ndcb1 = (((column>>1) & 0xff) |
-			 ((page_addr<<8) & 0xff00) |
-			 ((page_addr<<8) & 0xff0000) |
-			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_READ1:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
-		goto end;
-	case NAND_CMD_READOOB:
-		DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
-		goto end;
-	case NAND_CMD_READID:
-		dfc_new_cmd();
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
-		ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_PAGEPROG:
-		/* sent as a multicommand in NAND_CMD_SEQIN */
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
-		goto end;
-	case NAND_CMD_ERASE1:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		dfc_new_cmd();
-		ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
-		ndcb1 = (page_addr & 0x00ffffff);
-		goto write_cmd;
-	case NAND_CMD_ERASE2:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
-		goto end;
-	case NAND_CMD_SEQIN:
-		/* send PAGE_PROG command(0x1080) */
-		dfc_new_cmd();
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
-		column >>= 1; /* adjust for 16 bit bus */
-		ndcb1 = (((column>>1) & 0xff) |
-			 ((page_addr<<8) & 0xff00) |
-			 ((page_addr<<8) & 0xff0000) |
-			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
-		event = NDSR_WRDREQ;
-		goto write_cmd;
-	case NAND_CMD_STATUS:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
-		dfc_new_cmd();
-		ndcb0 = NAND_CMD_STATUS | (4<<21);
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_RESET:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
-		ndcb0 = NAND_CMD_RESET | (5<<21);
-		event = NDSR_CS0_CMDD;
-		goto write_cmd;
-	default:
-		printk("dfc_cmdfunc: error, unsupported command.\n");
-		goto end;
-	}
-
- write_cmd:
-	writel(ndcb0, NDCB0);
-	writel(ndcb1, NDCB0);
-	writel(ndcb2, NDCB0);
-
-	/*  wait_event: */
-	dfc_wait_event(event);
- end:
-	return;
-}
-
-static void dfc_gpio_init(void)
-{
-	DFC_DEBUG2("Setting up DFC GPIO's.\n");
-
-	/* no idea what is done here, see zylonite.c */
-	writel(0x1, GPIO4);
-
-	writel(0x00000001, DF_ALE_nWE1);
-	writel(0x00000001, DF_ALE_nWE2);
-	writel(0x00000001, DF_nCS0);
-	writel(0x00000001, DF_nCS1);
-	writel(0x00000001, DF_nWE);
-	writel(0x00000001, DF_nRE);
-	writel(0x00000001, DF_IO0);
-	writel(0x00000001, DF_IO8);
-	writel(0x00000001, DF_IO1);
-	writel(0x00000001, DF_IO9);
-	writel(0x00000001, DF_IO2);
-	writel(0x00000001, DF_IO10);
-	writel(0x00000001, DF_IO3);
-	writel(0x00000001, DF_IO11);
-	writel(0x00000001, DF_IO4);
-	writel(0x00000001, DF_IO12);
-	writel(0x00000001, DF_IO5);
-	writel(0x00000001, DF_IO13);
-	writel(0x00000001, DF_IO6);
-	writel(0x00000001, DF_IO14);
-	writel(0x00000001, DF_IO7);
-	writel(0x00000001, DF_IO15);
-
-	writel(0x1901, DF_nWE);
-	writel(0x1901, DF_nRE);
-	writel(0x1900, DF_CLE_nOE);
-	writel(0x1901, DF_ALE_nWE1);
-	writel(0x1900, DF_INT_RnB);
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand_new.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
-
-	/* set up GPIO Control Registers */
-	dfc_gpio_init();
-
-	/* turn on the NAND Controller Clock (104 MHz @ D0) */
-	writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
-
-#undef CONFIG_SYS_TIMING_TIGHT
-#ifndef CONFIG_SYS_TIMING_TIGHT
-	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tCH);
-	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tCS);
-	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tWH);
-	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tWP);
-	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tRH);
-	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tRP);
-	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
-		 DFC_MAX_tR);
-	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
-		   DFC_MAX_tWHR);
-	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tAR);
-#else /* this is the tight timing */
-
-	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
-		  DFC_MAX_tCH);
-	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
-		  DFC_MAX_tCS);
-	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
-		  DFC_MAX_tWH);
-	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
-		  DFC_MAX_tWP);
-	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
-		  DFC_MAX_tRH);
-	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
-		  DFC_MAX_tRP);
-	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
-		 DFC_MAX_tR);
-	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
-		   DFC_MAX_tWHR);
-	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
-		  DFC_MAX_tAR);
-#endif /* CONFIG_SYS_TIMING_TIGHT */
-
-
-	DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
-
-	/* tRP value is split in the register */
-	if(tRP & (1 << 4)) {
-		tRP_high = 1;
-		tRP &= ~(1 << 4);
-	} else {
-		tRP_high = 0;
-	}
-
-	writel((tCH << 19) |
-		(tCS << 16) |
-		(tWH << 11) |
-		(tWP << 8) |
-		(tRP_high << 6) |
-		(tRH << 3) |
-		(tRP << 0),
-		NDTR0CS0);
-
-	writel((tR << 16) |
-		(tWHR << 4) |
-		(tAR << 0),
-		NDTR1CS0);
-
-	/* If it doesn't work (unlikely) think about:
-	 *  - ecc enable
-	 *  - chip select don't care
-	 *  - read id byte count
-	 *
-	 * Intentionally enabled by not setting bits:
-	 *  - dma (DMA_EN)
-	 *  - page size = 512
-	 *  - cs don't care, see if we can enable later!
-	 *  - row address start position (after second cycle)
-	 *  - pages per block = 32
-	 *  - ND_RDY : clears command buffer
-	 */
-	/* NDCR_NCSX |		/\* Chip select busy don't care *\/ */
-
-	writel(NDCR_SPARE_EN |		/* use the spare area */
-		NDCR_DWIDTH_C |		/* 16bit DFC data bus width  */
-		NDCR_DWIDTH_M |		/* 16 bit Flash device data bus width */
-		(2 << 16) |		/* read id count = 7 ???? mk@tbd */
-		NDCR_ND_ARB_EN |	/* enable bus arbiter */
-		NDCR_RDYM |		/* flash device ready ir masked */
-		NDCR_CS0_PAGEDM |	/* ND_nCSx page done ir masked */
-		NDCR_CS1_PAGEDM |
-		NDCR_CS0_CMDDM |	/* ND_CSx command done ir masked */
-		NDCR_CS1_CMDDM |
-		NDCR_CS0_BBDM |		/* ND_CSx bad block detect ir masked */
-		NDCR_CS1_BBDM |
-		NDCR_DBERRM |		/* double bit error ir masked */
-		NDCR_SBERRM |		/* single bit error ir masked */
-		NDCR_WRDREQM |		/* write data request ir masked */
-		NDCR_RDDREQM |		/* read data request ir masked */
-		NDCR_WRCMDREQM,		/* write command request ir masked */
-		NDCR);
-
-
-	/* wait 10 us due to cmd buffer clear reset */
-	/*	wait(10); */
-
-
-	nand->cmd_ctrl = dfc_hwcontrol;
-/*	nand->dev_ready = dfc_device_ready; */
-	nand->ecc.mode = NAND_ECC_SOFT;
-	nand->ecc.layout = &delta_oob;
-	nand->options = NAND_BUSWIDTH_16;
-	nand->waitfunc = dfc_wait;
-	nand->read_byte = dfc_read_byte;
-	nand->read_word = dfc_read_word;
-	nand->read_buf = dfc_read_buf;
-	nand->write_buf = dfc_write_buf;
-
-	nand->cmdfunc = dfc_cmdfunc;
-	nand->badblock_pattern = &delta_bbt_descr;
-	return 0;
-}
-
-#endif

board/innokom/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= innokom.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/innokom/config.mk

@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000

board/innokom/innokom.c

@@ -100,8 +100,9 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
 	gd->bd->bi_boot_params = 0xa0000100;
@@ -110,22 +111,20 @@ int board_init (void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
-
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
-
 /**
  * innokom_set_led: - switch LEDs on or off
  *

board/innokom/lowlevel_init.S

@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
-/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
-/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/*	ldr	r1,	=LED_BLANK */
-/*	mov	r0,	#0xFF */
-/*	str	r0,	[r1]		/  turn on hex leds */
-/* */
-/*loop: */
-/* */
-/*   ldr	r0, =0xB0070001 */
-/*   ldr	r1, =_LED */
-/*   str	r0, [r1]		/  hex display */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
-	adr	r3, mem_init		/* r0 <- current position of code   */
-	ldr	r2, =mem_init
-	cmp	r3, r2			/* skip init if in place            */
-	beq	initirqs
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	ldr	r2,	=0xFFF
-	and	r3,	r3, r2
-	ldr	r4,	=0x03ca4000
-	orr	r4,	r4,  r3
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,	[r1, #MDREFR_OFFSET]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* Step 4a: assert MDREFR:K?RUN and configure                       */
-	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
-
-	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4, #(MDREFR_SLFRSH)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
-
-	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	/*          There should 9 writes, since the first write doesn't    */
-	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
-	/*          PXA210 Processors Specification Update,                 */
-	/*          Jan 2003, Errata #116, page 30.                         */
-
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr	r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str	r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-/*
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-*/
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size                                                  */
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR			/* enable no sources        */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#ifndef DEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr

board/lubbock/Makefile

@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= lubbock.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/lubbock/config.mk

@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0

board/lubbock/lowlevel_init.S

@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
-	ldr     r2,     =0xFFF
-	and     r3,     r3,  r2
-	ldr	r4,	=0x03ca4000
-	orr     r4,     r4,  r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4                            */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	orr	r4,	r4,	#(MDREFR_SLFRSH)
-	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	    str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-    ldr     r1, =DRAM_SIZE
-	 str	   r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-    ldr	r0, =ICMR /* enable no sources */
-	mov r1, #0
-    str r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr

board/lubbock/lubbock.c

@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
@@ -55,19 +56,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET

board/palmld/Makefile

@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= palmld.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/palmld/config.mk

@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000

board/palmld/lowlevel_init.S

@@ -1,45 +0,0 @@
-/*
- * Palm LifeDrive Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-
-	/* Enable GPIO reset */
-	ldr	r0, =PCFR
-	mov	r1, #0x30
-	str	r1, [r0]
-
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr

board/palmld/palmld.c

@@ -33,7 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	/* arch number of Lubbock-Board */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of PalmLD */
 	gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
 
 	/* adress of boot parameters */
@@ -52,12 +56,18 @@ struct serial_device *default_serial_console(void)
 	return &serial_ffuart_device;
 }
 
+extern void pxa_dram_init(void);
 int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)

board/palmld/u-boot.lds

@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  cpu/pxa/start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}

board/palmtc/Makefile

@@ -24,17 +24,16 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= palmtc.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/palmtc/config.mk

@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000

board/palmtc/lowlevel_init.S

@@ -1,39 +0,0 @@
-/*
- * Palm Tungsten|C Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr

board/palmtc/palmtc.c

@@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	/* Arch number of Palm Tungsten|C */
 	gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
 
@@ -51,9 +55,16 @@ struct serial_device *default_serial_console(void)
 	return &serial_ffuart_device;
 }
 
+extern void pxa_dram_init(void);
 int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	return 0;
 }

board/palmtc/u-boot.lds

@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  cpu/pxa/start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}

board/pleb2/Makefile

@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= pleb2.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/pleb2/config.mk

@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =  0xa1F80000
-#CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0

board/pleb2/lowlevel_init.S

@@ -1,488 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-	.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	/* Set up GPIO pins first */
-
-	ldr	r0,   =GPSR0
-	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR1
-	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR2
-	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR0
-	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR1
-	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR2
-	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER0
-	ldr	r1,   =CONFIG_SYS_GRER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER1
-	ldr	r1,   =CONFIG_SYS_GRER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER2
-	ldr	r1,   =CONFIG_SYS_GRER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER0
-	ldr	r1,   =CONFIG_SYS_GFER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER1
-	ldr	r1,   =CONFIG_SYS_GFER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER2
-	ldr	r1,   =CONFIG_SYS_GFER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR0
-	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR1
-	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR2
-	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
-	str	r1,   [r0]
-
-	/* enable GPIO pins */
-	ldr	r0,   =PSSR
-	ldr	r1,   =CONFIG_SYS_PSSR_VAL
-	str	r1,   [r0]
-
-
-/*********************************************************************
-    Initlialize Memory Controller
-
-    See PXA250 Operating System Developer's Guide
-
-    pause for 200 uSecs- allow internal clocks to settle
-    *Note: only need this if hard reset... doing it anyway for now
-*/
-
-	@ Step 1
-	@ ---- Wait 200 usec
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-	@ get memory controller base address
-	ldr	r1,  =MEMC_BASE
-
-@****************************************************************************
-@  Step 2
-@
-
-	@ Step 2a
-	@ write msc0, read back to ensure data latches
-	@
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]
-
-	@ write msc1
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	@ write msc2
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-
-@ Step 2b
-	@ write mecr
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-
-	@ write mcmem0
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-
-	@ write mcmem1
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-
-	@ write mcatt0
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-
-	@ write mcatt1
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-
-	@ write mcio0
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-
-	@ write mcio1
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-
-@ Step 2c
-	@ fly-by-dma is defeatured on this part
-	@ write flycnfg
-	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	@str	r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ extract DRI field (we need a valid DRI field)
-	@
-	ldr	r2,  =0xFFF
-
-	@ valid DRI field in r3
-	@
-	and	r3,  r3,  r2
-
-	@ get the reset state of MDREFR
-	@
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ clear the DRI field
-	@
-	bic	r4,  r4,  r2
-
-	@ insert the valid DRI field loaded above
-	@
-	orr	r4,  r4,  r3
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-	mov	pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-	@ clear the free-running clock bits
-	@ (clear K0Free, K1Free, K2Free
-	@
-	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4,  #0x00002000
-
-	@ set K1RUN if bank 0 installed
-	@
-	orr	r4,  r4,  #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#else
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@  Step 4
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4,  #0x00002000
-
-	@ set K1RUN for bank 0
-	@
-	orr	r4,  r4,  #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#endif
-
-	@ Step 4d
-	@ fetch platform value of mdcnfg
-	@
-	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic	r2,  r2,  #MDCNFG_DWID0	     @0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str	r2,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4e
-	@ pause for 200 uSecs
-	@
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-	1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/* Why is this here??? */
-	mov	r0, #0x78		 @turn everything off
-	mcr	p15, 0, r0, c1, c0, 0	   @(caches off, MMU off, etc.)
-
-	@ Step 4f
-	@ Access memory *not yet enabled* for CBR refresh cycles (8)
-	@ - CBR is generated for all banks
-
-	ldr	r2, =CONFIG_SYS_DRAM_BASE
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-
-	@ Step 4g
-	@get memory controller base address
-	@
-	ldr	r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr	r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr	r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str	r3,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4h
-	@ write mdmrs
-	@
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	@ Done Memory Init
-
-	/*SET_LED 6 */
-
-	@********************************************************************
-	@ Disable (mask) all interrupts at the interrupt controller
-	@
-
-	@ clear the interrupt level register (use IRQ, not FIQ)
-	@
-	mov	r1, #0
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	@ Set interrupt mask register
-	@
-	ldr	r1,  =CONFIG_SYS_ICMR_VAL
-	ldr	r2,  =ICMR
-	str	r1,  [r2]
-
-	@ ********************************************************************
-	@ Disable the peripheral clocks, and set the core clock
-	@
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-	ldr	r1,  =CKEN
-	mov	r2,  #0
-	str	r2,  [r1]
-
-	@ set core clocks
-	@
-	ldr	r2,  =CONFIG_SYS_CCCR_VAL
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-	#ifdef ENABLE32KHZ
-	@ enable the 32Khz oscillator for RTC and PowerManager
-	@
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	@ NOTE:	 spin here until OSCC.OOK get set,
-	@	 meaning the PLL has settled.
-	@
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#endif
-
-	@ Turn on needed clocks
-	@
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN_VAL
-	str	r2,  [r1]
-
-	/*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-   /*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	mov	pc, r10
-
-@ End lowlevel_init

board/pleb2/pleb2.c

@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
@@ -55,17 +56,16 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }

board/pxa255_idp/Makefile

@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= pxa_idp.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/pxa255_idp/config.mk

@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0

board/pxa255_idp/lowlevel_init.S

@@ -1,496 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-/*
- *	Memory setup
- */
-.globl lowlevel_init
-lowlevel_init:
-
-	mov      r10, lr
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 3rd blink */
-	bl	blink
-#endif
-
-	/* Set up GPIO pins first ----------------------------------------- */
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 4th debug blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 5th blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
-	ldr     r2,     =0xFFF
-	and     r3,     r3,  r2
-	ldr	r4,	=0x03ca4000
-	orr     r4,     r4,  r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4                            */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	orr	r4,	r4,	#(MDREFR_SLFRSH)
-	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	    str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-	/* We are finished with Intel's memory controller initialisation    */
-#if 0
-	/* FIXME turn on serial ports */
-	/* look into moving this to board_init() */
-	ldr	r2, =(PXA_CS5_PHYS + 0x03C0002c)
-	mov	r3, #0x13
-	str	r3, [r2]
-#endif
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 6th blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-#if 0
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#endif
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-	ldr     r1, =DRAM_SIZE
-	str     r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR /* enable no sources */
-	mov r1, #0
-	str r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
-	/* ---------------------------------------------------------------- */
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 7th blink */
-	bl	blink
-#endif
-
-endlowlevel_init:
-
-	mov     pc, r10
-
-
-#ifdef DEBUG_BLINK_ENABLE
-
-/* debug LED code */
-
-/* delay about 200ms */
-delay:
-
-	/* reset OSCR to 0 */
-	ldr	r8, =OSCR
-	mov	r9, #0
-	str	r9, [r8]
-
-	/* make sure new value has stuck */
-1:
-	ldr	r8, =OSCR
-	ldr	r9, [r8]
-	mov	r8, #0x10000
-	cmp	r9, r8
-	bgt	1b
-
-	/* now, wait for delay to expire */
-1:
-	ldr	r8, =OSCR
-	ldr	r9, [r8]
-	mov	r8, #0xd4000
-	cmp	r8, r9
-	bgt	1b
-
-	mov	pc, lr
-
-/* blink code -- trashes r7, r8, r9 */
-
-.globl blink
-blink:
-
-	mov	r7, lr
-
-	/* set GPIO10 as outout */
-	ldr	r8,  =GPDR0
-	ldr	r9,  [r8]
-	orr	r9,  r9, #(1<<10)
-	str	r9,  [r8]
-
-	/* turn LED off */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPCR0
-	str	r9, [r8]
-	bl	delay
-
-	/* turn LED on */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPSR0
-	str	r9, [r8]
-	bl	delay
-
-	/* turn LED off */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPCR0
-	str	r9, [r8]
-
-	mov	pc, r7
-
-#endif

board/pxa255_idp/pxa_idp.c

@@ -43,8 +43,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
@@ -82,22 +83,20 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
-
 #ifdef DEBUG_BLINKC_ENABLE
 
 void delay_c(void)

board/renesas/sh7785lcr/config.mk

@@ -24,6 +24,8 @@
 #
 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
-ifndef CONFIG_SYS_TEXT_BASE
+ifdef CONFIG_SH_32BIT
+CONFIG_SYS_TEXT_BASE = 0x8FF80000
+else
 CONFIG_SYS_TEXT_BASE = 0x0ff80000
 endif

board/trizepsiv/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= conxs.o eeprom.o
-SOBJS	:= lowlevel_init.o pxavoltage.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/trizepsiv/config.mk

@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =0xa1f00000
-# 0xa1700000
-#CONFIG_SYS_TEXT_BASE = 0

board/trizepsiv/conxs.c

@@ -104,8 +104,9 @@ void usb_board_stop(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of ConXS Board */
 	gd->bd->bi_arch_number = 776;
@@ -138,18 +139,18 @@ struct serial_device *default_serial_console (void)
 	return &serial_ffuart_device;
 }
 
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_DRIVER_DM9000

board/trizepsiv/lowlevel_init.S

@@ -1,503 +0,0 @@
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc	p15,0,\reg,c2,c0,0
-   mov	\reg,\reg
-   sub	pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR3
-	ldr		r1,	=CONFIG_SYS_GPSR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR3
-	ldr		r1,	=CONFIG_SYS_GPCR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER0
-	ldr		r1,	=CONFIG_SYS_GRER0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER1
-	ldr		r1,	=CONFIG_SYS_GRER1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER2
-	ldr		r1,	=CONFIG_SYS_GRER2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER3
-	ldr		r1,	=CONFIG_SYS_GRER3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER0
-	ldr		r1,	=CONFIG_SYS_GFER0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER1
-	ldr		r1,	=CONFIG_SYS_GFER1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER2
-	ldr		r1,	=CONFIG_SYS_GFER2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER3
-	ldr		r1,	=CONFIG_SYS_GFER3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR3
-	ldr		r1,	=CONFIG_SYS_GPDR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR3_L
-	ldr		r1,	=CONFIG_SYS_GAFR3_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR3_U
-	ldr		r1,	=CONFIG_SYS_GAFR3_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface					    */
-	/*								    */
-	/* The sequence below is based on the recommended init steps	    */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.							    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
-	/*	   clocks to settle. Only necessary after hard reset...	    */
-	/*	   FIXME: can be optimized later			    */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty	    */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller	    */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type			    */
-
-	/* MSC0: nCS(0,1)						    */
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
-						/* that data latches	    */
-	/* MSC1: nCS(2,3)						    */
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)						    */
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface				    */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register				    */
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing				    */
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing				    */
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
-	/* ---------------------------------------------------------------- */
-	ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	str	r2,  [r1, #FLYCNFG_OFFSET]
-	str	r2,	[r1, #FLYCNFG_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
-	/* this to power on defaults + DRI field.			    */
-
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-	ldr	r2,	=0xFFF
-	bic	r4,	r4, r2
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	and	r3,	r3,  r2
-
-	orr	r4,	r4, r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
-
-	orr	r4,  r4, #MDREFR_K0RUN
-	orr	r4,  r4, #MDREFR_K0DB4
-	orr	r4,  r4, #MDREFR_K0FREE
-	orr	r4,  r4, #MDREFR_K0DB2
-	orr	r4,  r4, #MDREFR_K1DB2
-	bic	r4,  r4, #MDREFR_K1FREE
-	bic	r4,  r4, #MDREFR_K2FREE
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4			    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits		    */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.						    */
-
-	ldr	r2,  =CONFIG_SYS_SXCNFG_VAL
-	str	r2,  [r1, #SXCNFG_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM					    */
-	/* ---------------------------------------------------------------- */
-
-	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
-	orr	r4, r4, #MDREFR_K1RUN
-	bic	r4, r4, #MDREFR_K2DB2
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	bic	r4, r4, #MDREFR_SLFRSH
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	orr	r4, r4, #MDREFR_E1PIN
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	nop
-	nop
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*	    configure but not enable each SDRAM partition pair.	    */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
-
-	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
-	ldr	r4,	[r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
-	/*	    100..200 µsec.					    */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty	    */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
-	/*	    attempting non-burst read or write accesses to disabled */
-	/*	    SDRAM, as commonly specified in the power up sequence   */
-	/*	    documented in SDRAM data sheets. The address(es) used   */
-	/*	    for this purpose must not be cacheable.		    */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted		    */
-	/*	    (MDCNFG:DEx set to 1).				    */
-
-	ldr	r3,	[r1, #MDCNFG_OFFSET]
-	mov	r4, r3
-	orr	r3,	r3,	#MDCNFG_DE0
-	str	r3,	[r1, #MDCNFG_OFFSET]
-	mov	r0, r3
-
-	/* Step 4h: Write MDMRS.					    */
-
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	/* enable APD */
-	ldr	r3,  [r1, #MDREFR_OFFSET]
-	orr	r3,  r3,  #MDREFR_APD
-	str	r3,  [r1, #MDREFR_OFFSET]
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-setvoltage:
-
-	mov	r10,	lr
-	bl	initPXAvoltage	/* In case the board is rebooting with a    */
-	mov	lr,	r10	/* low voltage raise it up to a good one.   */
-
-#if 1
-	b initirqs
-#endif
-
-wakeup:
-	/* Are we waking from sleep? */
-	ldr	r0,	=RCSR
-	ldr	r1,	[r0]
-	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
-	str	r1,	[r0]
-	teq	r1,	#RCSR_SMR
-
-	bne	initirqs
-
-	ldr	r0,	=PSSR
-	mov	r1,	#PSSR_PH
-	str	r1,	[r0]
-
-	/* if so, resume at PSPR */
-	ldr	r0,	=PSPR
-	ldr	r1,	[r0]
-	mov	pc,	r1
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller	    */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
-	str	r1,  [r2]
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation						    */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-
-	/* Turn Off on-chip peripheral clocks (except for memory)	    */
-	/* for re-configuration.					    */
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN
-	str	r2,  [r1]
-
-	/* ... and write the core clock config register			    */
-	ldr	r2,  =CONFIG_SYS_CCCR
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-	/* Turn on turbo mode */
-	mrc	p14, 0, r2, c6, c0, 0
-	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
-	mcr	p14, 0, r2, c6, c0, 0
-
-	/* Re-write MDREFR */
-	ldr	r1, =MEMC_BASE
-	ldr	r2, [r1, #MDREFR_OFFSET]
-	str	r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager		    */
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
-	/* has settled.							    */
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#else
-#error "RTC not defined"
-#endif
-
-	/* Interrupt init: Mask all interrupts				    */
-    ldr r0, =ICMR /* enable no sources */
-	mov r1, #0
-    str r1, [r0]
-	/* FIXME */
-
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init							    */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov	pc, lr

board/ttcontrol/vision2/vision2.c

@@ -37,14 +37,34 @@
 #include <fsl_esdhc.h>
 #include <fsl_pmic.h>
 #include <mc13892.h>
+#include <linux/fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static u32 system_rev;
 
+extern int mx51_fb_init(struct fb_videomode *mode);
+
 #ifdef CONFIG_HW_WATCHDOG
 #include <watchdog.h>
 
+static struct fb_videomode nec_nl6448bc26_09c = {
+	"NEC_NL6448BC26-09C",
+	60,	/* Refresh */
+	640,	/* xres */
+	480,	/* yres */
+	37650,	/* pixclock = 26.56Mhz */
+	48,	/* left margin */
+	16,	/* right margin */
+	31,	/* upper margin */
+	12,	/* lower margin */
+	96,	/* hsync-len */
+	2,	/* vsync-len */
+	0,	/* sync */
+	FB_VMODE_NONINTERLACED,	/* vmode */
+	0,	/* flag */
+};
+
 void hw_watchdog_reset(void)
 {
 	int val;
@@ -423,6 +443,9 @@ static void setup_gpios(void)
 	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
 	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
 
+	/* PWM Output GPIO1_2 */
+	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+
 	/*
 	 * Set GPIO1_4 to high and output; it is used to reset
 	 * the system on reboot
@@ -630,6 +653,33 @@ int board_early_init_f(void)
 	return 0;
 }
 
+static void backlight(int on)
+{
+	if (on) {
+		mxc_gpio_set(65, 1);
+		udelay(10000);
+		mxc_gpio_set(68, 1);
+	} else {
+		mxc_gpio_set(65, 0);
+		mxc_gpio_set(68, 0);
+	}
+}
+
+void lcd_enable(void)
+{
+	int ret;
+
+	mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+
+	mxc_gpio_set(2, 1);
+	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+
+	ret = mx51_fb_init(&nec_nl6448bc26_09c);
+	if (ret)
+		puts("LCD cannot be configured\n");
+}
+
 int board_init(void)
 {
 #ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
@@ -709,3 +759,21 @@ int checkboard(void)
 	return 0;
 }
 
+int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int on;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	on = (strcmp(argv[1], "on") == 0);
+	backlight(on);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
+	"Vision2 Backlight",
+	"lcdbl [on|off]\n"
+);

board/wepep250/Makefile

@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= wepep250.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

board/wepep250/config.mk

@@ -1,11 +0,0 @@
-#
-# This is config used for compilation of WEP EP250 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
-#CONFIG_SYS_TEXT_BASE = 0xa1001000

board/wepep250/flash.c

@@ -1,324 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- *       hopefully may work with other configurations.
- */
-
-#if ( WEP_FLASH_BUS_WIDTH == 1 )
-#  define FLASH_BUS vu_char
-#  define FLASH_BUS_RET u_char
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  else
-#    error "With 8bit bus only one chip is allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 2 )
-#  define FLASH_BUS vu_short
-#  define FLASH_BUS_RET u_short
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 8 )| x )
-#  else
-#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 4 )
-#  define FLASH_BUS vu_long
-#  define FLASH_BUS_RET u_long
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 16 )| x )
-#  elif ( WEP_FLASH_INTERLEAVE == 4 )
-#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-#  else
-#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-#  endif
-
-#else
-#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
-	FLASH_BUS *addr = (FLASH_BUS *) 0;
-
-	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
-	return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
-	int ok = 1;
-
-	reset_timer_masked ();
-	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
-		   FLASH_CMD (CFI_INTEL_SR_READY)) {
-		if (get_timer_masked () > timeout && timeout != 0) {
-			ok = 0;
-			break;
-		}
-	}
-	return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-#  error "WEP platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
-	int i;
-	FLASH_BUS address = WEP_FLASH_BASE;
-
-	flash_info[0].size = WEP_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
-		flash_info[0].start[i] = address;
-#ifdef WEP_FLASH_UNLOCK
-		/* Some devices are hw locked after start. */
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
-		flash_ready (0);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
-		address += WEP_FLASH_SECT_SIZE;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_SYS_FLASH_BASE,
-				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-				   &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_ENV_ADDR,
-				   CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return WEP_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	printf (" Intel vendor\n");
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if (!(i % 5)) {
-			printf ("\n");
-		}
-
-		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, non_protected = 0, sector;
-	int rc = ERR_OK;
-
-	FLASH_BUS *address;
-
-	for (sector = s_first; sector <= s_last; sector++) {
-		if (!info->protect[sector]) {
-			non_protected++;
-		}
-	}
-
-	if (!non_protected) {
-		return ERR_PROTECTED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts ();
-
-
-	/* Start erase on unprotected sectors */
-	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
-		if (info->protect[sector]) {
-			printf ("Protected sector %2d skipping...\n", sector);
-			continue;
-		} else {
-			printf ("Erasing sector %2d ... ", sector);
-		}
-
-		address = (FLASH_BUS *) (info->start[sector]);
-
-		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
-		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
-			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-			printf ("ok.\n");
-		} else {
-			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-			rc = ERR_TIMOUT;
-			printf ("timeout! Aborting...\n");
-			break;
-		}
-		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	}
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
-	FLASH_BUS *address = (FLASH_BUS *) dest;
-	int rc = ERR_OK;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*address & data) != data) {
-		return ERR_NOT_ERASED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts ();
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
-	*address = data;
-
-	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
-		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-		rc = ERR_TIMOUT;
-		printf ("timeout! Aborting...\n");
-	}
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong read_addr, write_addr;
-	FLASH_BUS data;
-	int i, result = ERR_OK;
-
-
-	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
-	write_addr = read_addr;
-	if (read_addr != addr) {
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (read_addr < addr || cnt == 0) {
-				data |= *((uchar *) read_addr) << i * 8;
-			} else {
-				data |= (*src++) << i * 8;
-				cnt--;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-	}
-	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
-		if ((result = write_data (info, write_addr,
-								  *((FLASH_BUS *) src))) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-		src += sizeof (FLASH_BUS);
-	}
-	if (cnt > 0) {
-		read_addr = write_addr;
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (cnt > 0) {
-				data |= (*src++) << i * 8;
-				cnt--;
-			} else {
-				data |= *((uchar *) read_addr) << i * 8;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != 0) {
-			return result;
-		}
-	}
-	return ERR_OK;
-}

board/wepep250/intel.h

@@ -1,99 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef	FLASH_INTEL_H
-#define	FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define	CFI_CHIP_INTEL_28F320J3A		0x0016
-#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
-#define	CFI_CHIP_INTEL_28F640J3A		0x0017
-#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
-#define	CFI_CHIP_INTEL_28F128J3A		0x0018
-#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define	CFI_CHIP_INTEL_28F640K3			0x8801
-#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
-#define	CFI_CHIP_INTEL_28F128K3			0x8802
-#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
-#define	CFI_CHIP_INTEL_28F256K3			0x8803
-#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
-#define	CFI_CHIP_INTEL_28F640K18		0x8805
-#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
-#define	CFI_CHIP_INTEL_28F128K18		0x8806
-#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
-#define	CFI_CHIP_INTEL_28F256K18		0x8807
-#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
-
-#endif /* FLASH_INTEL_H */

board/wepep250/lowlevel_init.S

@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- *     Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- *     Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- *     Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-/*	setup memory - see 6.12 in [1]
- *	Step 1	- wait 200 us
- */
-	mov	r0,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r0, r0, #1
-	bne	1b
-/*	TODO: complete step 1 for Synchronous Static memory*/
-
-	ldr	r0, =0x48000000			/* MC_BASE */
-
-
-/*	step 1.a - setup MSCx
- */
-	ldr	r1, =0x000012B3			/* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
-	str	r1, [r0, #0x8]			/* MSC0_OFFSET */
-
-/*	step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- *	see AUTO REFRESH chapter in section D. in [2] and in [3]
- *	DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- *	DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- *	TODO: complete for Synchronous Static memory
- */
-	ldr	r1, [r0, #4]			/* MDREFR_OFFSET */
-	ldr	r2, =0x01000FFF			/* MDREFR_K1FREE | MDREFR_DRI_MASK */
-	bic	r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
-	orr	r1, r1, #48			/* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
-	orr	r1, r1, #24			/* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 2 - only for Synchronous Static memory (TODO)
- *
- *	Step 3 - same as step 4
- *
- *	Step 4
- *
- *	Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
-	orr	r1, r1, #0x00010000		/* MDREFR_K1RUN */
-	bic	r1, r1, #0x00020000		/* MDREFR_K1DB2 */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.b - clear MDREFR:SLFRSH */
-	bic	r1, r1, #0x00400000		/* MDREFR_SLFRSH */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.c - set MDREFR:E1PIN */
-	orr	r1, r1, #0x00008000		/* MDREFR_E1PIN */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.d - automatically done
- *
- *	Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
-	ldr	r1, =0x00000AA8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
-	ldr	r1, =0x00000AC8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 5 - wait at least 200 us for SDRAM
- *	see section B. in [2]
- */
-	mov	r2,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r2, r2, #1
-	bne	1b
-
-/*	Step 6 - after reset dcache is disabled, so automatically done
- *
- *	Step 7 - eight refresh cycles
- */
-	mov	r2, #0xA0000000
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-
-/*	Step 8 - we don't need dcache now
- *
- *	Step 9 - enable SDRAM partition 0
- */
-	orr	r1, r1, #1			/* MDCNFG_DE0 */
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 10 - write MDMRS */
-	mov	r1, #0
-	str	r1, [r0, #0x40]			/* MDMRS_OFFSET */
-
-/*	Step 11 - optional (TODO) */
-
-	mov	pc,r10

board/wepep250/wepep250.c

@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
-	gd->bd->bi_boot_params = 0xa0000000;
-/*
- * Setup GPIO stuff to get serial working
- */
-#if defined( CONFIG_FFUART )
-	writel(0x80, GPDR1);
-	writel(0x8010, GAFR1_L);
-#elif defined( CONFIG_BTUART )
-	writel(0x800, GPDR1);
-	writel(0x900000, GAFR1_L);
-#endif
-	writel(0x20, PSSR);
-
-	return 0;
-}
-
-int dram_init (void)
-{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
-	gd->bd->bi_dram[0].start = WEP_SDRAM_1;
-	gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
-	gd->bd->bi_dram[1].start = WEP_SDRAM_2;
-	gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
-	gd->bd->bi_dram[2].start = WEP_SDRAM_3;
-	gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
-	gd->bd->bi_dram[3].start = WEP_SDRAM_4;
-	gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
-#endif
-
-	return 0;
-}

board/xaeniax/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= xaeniax.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/xaeniax/config.mk

@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa3FB0000
-#CONFIG_SYS_TEXT_BASE = 0

board/xaeniax/lowlevel_init.S

@@ -1,424 +0,0 @@
- /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	 r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr	r0,=GPSR0
-	ldr	r1,=CONFIG_SYS_GPSR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPSR1
-	ldr	r1,=CONFIG_SYS_GPSR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPSR2
-	ldr	r1,=CONFIG_SYS_GPSR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR0
-	ldr	r1,=CONFIG_SYS_GPCR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR1
-	ldr	r1,=CONFIG_SYS_GPCR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR2
-	ldr	r1,=CONFIG_SYS_GPCR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR0
-	ldr	r1,=CONFIG_SYS_GPDR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR1
-	ldr	r1,=CONFIG_SYS_GPDR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR2
-	ldr	r1,=CONFIG_SYS_GPDR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR0_L
-	ldr	r1,=CONFIG_SYS_GAFR0_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR0_U
-	ldr	r1,=CONFIG_SYS_GAFR0_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR1_L
-	ldr	r1,=CONFIG_SYS_GAFR1_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR1_U
-	ldr	r1,=CONFIG_SYS_GAFR1_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR2_L
-	ldr	r1,=CONFIG_SYS_GAFR2_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR2_U
-	ldr	r1,=CONFIG_SYS_GAFR2_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=PSSR		/* enable GPIO pins */
-	ldr	r1,=CONFIG_SYS_PSSR_VAL
-	str	r1,[r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-
-	ldr	r1,=MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC0_VAL
-	str     r2,[r1, #MSC0_OFFSET]
-	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */
-
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC1_VAL
-	str     r2,[r1, #MSC1_OFFSET]
-	ldr     r2,[r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC2_VAL
-	str     r2,[r1, #MSC2_OFFSET]
-	ldr     r2,[r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,=CONFIG_SYS_MECR_VAL
-	str     r2,[r1, #MECR_OFFSET]
-	ldr	r2,[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,=CONFIG_SYS_MCMEM0_VAL
-	str     r2,[r1, #MCMEM0_OFFSET]
-	ldr	r2,[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,=CONFIG_SYS_MCMEM1_VAL
-	str     r2,[r1, #MCMEM1_OFFSET]
-	ldr	r2,[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,=CONFIG_SYS_MCATT0_VAL
-	str     r2,[r1, #MCATT0_OFFSET]
-	ldr	r2,[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,=CONFIG_SYS_MCATT1_VAL
-	str     r2,[r1, #MCATT1_OFFSET]
-	ldr	r2,[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,=CONFIG_SYS_MCIO0_VAL
-	str     r2,[r1, #MCIO0_OFFSET]
-	ldr	r2,[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,=CONFIG_SYS_MCIO1_VAL
-	str     r2,[r1, #MCIO1_OFFSET]
-	ldr	r2,[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	@ get the mdrefr settings
-	ldr     r4,=CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	str     r4,[r1, #MDREFR_OFFSET]
-	ldr     r4,[r1, #MDREFR_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	@ set K1RUN for bank 0
-	@
-	orr   r4,  r4,  #MDREFR_K1RUN
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic     r4,  r4,  #MDREFR_SLFRSH
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@ if E0PIN is also used:	 #(MDREFR_E1PIN|MDREFR_E0PIN)
-	orr     r4,  r4, #(MDREFR_E1PIN)
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-
-	/* Step 4d:							*/
-	/* fetch platform value of mdcnfg				*/
-	@
-	ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str     r2,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/* get memory controller base address                               */
-	ldr     r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr     r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,	=CONFIG_SYS_MDMRS_VAL
-	str     r2,	[r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r1,  =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
-	ldr     r2,  =ICMR
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value						    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	@ Turn on needed clocks
-	@
-test:
-	ldr     r1,  =CKEN
-	ldr     r2,  =CONFIG_SYS_CKEN_VAL
-	str     r2,  [r1]
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size ?*/
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov     pc, lr

board/xaeniax/xaeniax.c

@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of xaeniax */
 	gd->bd->bi_arch_number = 585;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	/*	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
-	/*	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
-	/*	gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
-	/*	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
-	/*	gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
-	/*	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET

board/xes/common/Makefile

@@ -32,7 +32,11 @@ LIB	= $(obj)lib$(VENDOR).a
 COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
 COBJS-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
 COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
+COBJS-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
 COBJS-$(CONFIG_FSL_DDR2)	+= fsl_8xxx_ddr.o
+COBJS-$(CONFIG_FSL_DDR3)	+= fsl_8xxx_ddr.o
+COBJS-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
 COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)

board/xes/common/board.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+	char name[] = CONFIG_SYS_BOARD_NAME;
+	char *s;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+	s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+	s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+	s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+	s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+	s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+	s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+	s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+	s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+	s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+	s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+	s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+	s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+	s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+	s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+	name[strlen(name) - 1] += get_board_derivative();
+	printf("Board: X-ES %s %s SBC\n", name, s);
+
+	/* Display board specific information */
+	puts("       ");
+	if ((s = getenv("board_rev")))
+		printf("Rev %s, ", s);
+	if ((s = getenv("serial#")))
+		printf("Serial# %s, ", s);
+	if ((s = getenv("board_cfg")))
+		printf("Cfg %s", s);
+	puts("\n");
+
+	return 0;
+}

board/xes/common/fsl_8xxx_clk.c

@@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy)
 	if (in_be32(&gur->gpporcr) & 0x10000)
 		return 66666666;
 	else
+#ifdef CONFIG_P2020
+		return 100000000;
+#else
 		return 50000000;
+#endif
 }
 
 #ifdef CONFIG_MPC85xx
@@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy)
 	if (ddr_ratio == 0x7)
 		return get_board_sys_clk(dummy);
 
+#ifdef CONFIG_P2020
+	if (in_be32(&gur->gpporcr) & 0x20000)
+		return 66666666;
+	else
+		return 100000000;
+#else
 	return 66666666;
+#endif
 }
 #endif

board/xes/common/fsl_8xxx_misc.c

@@ -0,0 +1,62 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+	if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_NVM_WP)
+		return 1;
+
+	return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number.  For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+       volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+       volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+       /*
+        * The top 4 lines of the local bus address are pulled low/high and
+        * can be read to determine the least significant digit of a board's
+        * model number.
+        */
+       return gur->gpporcr >> 28;
+}
+
+

board/trizepsiv/pxavoltage.S → board/xes/common/fsl_8xxx_misc.h

@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,9 +20,9 @@
  * MA 02111-1307 USA
  */
 
-#include <asm/arch/pxa-regs.h>
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
 
-		.global	initPXAvoltage
+uint get_board_derivative(void);
 
-initPXAvoltage:
-		mov	pc, lr
+#endif /* __FSL_8XXX_MISC_H__ */

board/xes/common/fsl_8xxx_pci.c

@@ -25,10 +25,10 @@
 #include <pci.h>
 #include <asm/fsl_pci.h>
 #include <asm/io.h>
+#include <linux/compiler.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
-int first_free_busno = 0;
 
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
@@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose;
 static struct pci_controller pcie3_hose;
 #endif
 
-#ifdef CONFIG_MPC8572
-/* Correlate host/agent POR bits to usable info. Table 4-14 */
-struct host_agent_cfg_t {
-	uchar pcie_root[3];
-	uchar rio_host;
-} host_agent_cfg[8] = {
-	{{0, 0, 0}, 0},
-	{{0, 1, 1}, 1},
-	{{1, 0, 1}, 0},
-	{{1, 1, 0}, 1},
-	{{0, 0, 1}, 0},
-	{{0, 1, 0}, 1},
-	{{1, 0, 0}, 0},
-	{{1, 1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-15 */
-struct io_port_cfg_t {
-	uchar pcie_width[3];
-	uchar rio_width;
-} io_port_cfg[16] = {
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{4, 0, 0}, 0},
-	{{4, 4, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 4},
-	{{4, 2, 2}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{4, 0, 0}, 4},
-	{{4, 0, 0}, 4},
-	{{0, 0, 0}, 4},
-	{{0, 0, 0}, 4},
-	{{8, 0, 0}, 0},
-};
-#elif defined CONFIG_MPC8548
-/* Correlate host/agent POR bits to usable info. Table 4-12 */
-struct host_agent_cfg_t {
-	uchar pci_host[2];
-	uchar pcie_root[1];
-	uchar rio_host;
-} host_agent_cfg[8] = {
-	{{1, 1}, {0}, 0},
-	{{1, 1}, {1}, 0},
-	{{1, 1}, {0}, 1},
-	{{0, 0}, {0}, 0}, /* reserved */
-	{{0, 1}, {1}, 0},
-	{{1, 1}, {1}, 0},
-	{{0, 1}, {1}, 1},
-	{{1, 1}, {1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-13 */
-struct io_port_cfg_t {
-	uchar pcie_width[1];
-	uchar rio_width;
-} io_port_cfg[8] = {
-	{{0}, 0},
-	{{0}, 0},
-	{{0}, 0},
-	{{4}, 4},
-	{{4}, 4},
-	{{0}, 4},
-	{{0}, 4},
-	{{8}, 0},
-};
-#elif defined CONFIG_MPC86xx
-/* Correlate host/agent POR bits to usable info. Table 4-17 */
-struct host_agent_cfg_t {
-	uchar pcie_root[2];
-	uchar rio_host;
-} host_agent_cfg[8] = {
-	{{0, 0}, 0},
-	{{1, 0}, 1},
-	{{0, 1}, 0},
-	{{1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-16 */
-struct io_port_cfg_t {
-	uchar pcie_width[2];
-	uchar rio_width;
-} io_port_cfg[16] = {
-	{{0, 0}, 0},
-	{{0, 0}, 0},
-	{{8, 0}, 0},
-	{{8, 8}, 0},
-	{{0, 0}, 0},
-	{{8, 0}, 4},
-	{{8, 0}, 4},
-	{{8, 0}, 4},
-	{{0, 0}, 0},
-	{{0, 0}, 4},
-	{{0, 0}, 4},
-	{{0, 0}, 4},
-	{{0, 0}, 0},
-	{{0, 0}, 0},
-	{{0, 8}, 0},
-	{{8, 8}, 0},
-};
-#endif
-
 /*
  * 85xx and 86xx share naming conventions, but different layout.
  * Correlate names to CPU-specific values to share common
@@ -173,22 +68,22 @@ struct io_port_cfg_t {
 
 void pci_init_board(void)
 {
-	struct pci_controller *hose;
-	volatile ccsr_fsl_pci_t *pci;
-	int width;
-	int host;
+	struct fsl_pci_info pci_info[3];
+	int first_free_busno = 0;
+	int num = 0;
+	int pcie_ep;
+	__maybe_unused int pcie_configured;
+
 #if defined(CONFIG_MPC85xx)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #elif defined(CONFIG_MPC86xx)
 	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 #endif
-	uint devdisr = in_be32(&gur->devdisr);
-	uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	__maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
 			MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
-	uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
-			MPC8xxx_PORBMSR_HA_SHIFT;
-	struct pci_region *r;
 
 #ifdef CONFIG_PCI1
 	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
@@ -197,49 +92,19 @@ void pci_init_board(void)
 	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
 	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
-	width = 0; /* Silence compiler warning... */
-	io_sel &= 0xf; /* Silence compiler warning... */
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	hose = &pci1_hose;
-	host = host_agent_cfg[host_agent].pci_host[0];
-	r = hose->regions;
-
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 		printf("\n    PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 			pci_32 ? 32 : 64,
 			pcix ? "PCIX" : "PCI",
 			pci_spd_norm ? ">=" : "<=",
 			pcix ? freq * 2 : freq,
-			host ? "host" : "agent",
+			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCI1_MEM_BASE,
-				CONFIG_SYS_PCI1_MEM_PHYS,
-				CONFIG_SYS_PCI1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCI1_IO_BASE,
-				CONFIG_SYS_PCI1_IO_PHYS,
-				CONFIG_SYS_PCI1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCI1 on bus %02x - %02x\n",
-			hose->first_busno, hose->last_busno);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 	} else {
 		printf("    PCI1: disabled\n");
 	}
@@ -247,148 +112,53 @@ void pci_init_board(void)
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
-#ifdef CONFIG_PCIE1
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	hose = &pcie1_hose;
-	host = host_agent_cfg[host_agent].pcie_root[0];
-	width = io_port_cfg[io_sel].pcie_width[0];
-	r = hose->regions;
-
-	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-		printf("\n    PCIE1 connected as %s (x%d)",
-			host ? "Root Complex" : "Endpoint", width);
-		if (in_be32(&pci->pme_msg_det)) {
-			out_be32(&pci->pme_msg_det, 0xffffffff);
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				in_be32(&pci->pme_msg_det));
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_MEM_BASE,
-				CONFIG_SYS_PCIE1_MEM_PHYS,
-				CONFIG_SYS_PCIE1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_IO_BASE,
-				CONFIG_SYS_PCIE1_IO_PHYS,
-				CONFIG_SYS_PCIE1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCIE1 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
+#ifdef CONFIG_PCIE1
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
+	} else {
+		printf("    PCIE1: disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	hose = &pcie2_hose;
-	host = host_agent_cfg[host_agent].pcie_root[1];
-	width = io_port_cfg[io_sel].pcie_width[1];
-	r = hose->regions;
-
-	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-		printf("\n    PCIE2 connected as %s (x%d)",
-			host ? "Root Complex" : "Endpoint", width);
-		if (in_be32(&pci->pme_msg_det)) {
-			out_be32(&pci->pme_msg_det, 0xffffffff);
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				in_be32(&pci->pme_msg_det));
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE2_MEM_BASE,
-				CONFIG_SYS_PCIE2_MEM_PHYS,
-				CONFIG_SYS_PCIE2_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE2_IO_BASE,
-				CONFIG_SYS_PCIE2_IO_PHYS,
-				CONFIG_SYS_PCIE2_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCIE2 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+		printf("    PCIE2 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie2_hose, first_free_busno);
+	} else {
+		printf("    PCIE2: disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
 #endif /* CONFIG_PCIE2 */
 
 #ifdef CONFIG_PCIE3
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
-	hose = &pcie3_hose;
-	host = host_agent_cfg[host_agent].pcie_root[2];
-	width = io_port_cfg[io_sel].pcie_width[2];
-	r = hose->regions;
-
-	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-		printf("\n    PCIE3 connected as %s (x%d)",
-			host ? "Root Complex" : "Endpoint", width);
-		if (in_be32(&pci->pme_msg_det)) {
-			out_be32(&pci->pme_msg_det, 0xffffffff);
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				in_be32(&pci->pme_msg_det));
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE3_MEM_BASE,
-				CONFIG_SYS_PCIE3_MEM_PHYS,
-				CONFIG_SYS_PCIE3_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE3_IO_BASE,
-				CONFIG_SYS_PCIE3_IO_PHYS,
-				CONFIG_SYS_PCIE3_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCIE3 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
+		SET_STD_PCIE_INFO(pci_info[num], 3);
+		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+		printf("    PCIE3 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie3_hose, first_free_busno);
+	} else {
+		printf("    PCIE3: disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);

board/xes/xpedite5170/xpedite5170.c → board/xes/xpedite517x/xpedite517x.c

@@ -26,30 +26,12 @@
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
 
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 #endif
 
-int checkboard(void)
-{
-	char *s;
-
-	printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	s = getenv("board_rev");
-	if (s)
-		printf("Rev %s, ", s);
-	s = getenv("serial#");
-	if (s)
-		printf("Serial# %s, ", s);
-	s = getenv("board_cfg");
-	if (s)
-		printf("Cfg %s", s);
-	printf("\n");
-
-	return 0;
-}
 /*
  * Print out which flash was booted from and if booting from the 2nd flash,
  * swap flash chip selects to maintain consistent flash numbering/addresses.

board/xes/xpedite5200/xpedite5200.c → board/xes/xpedite520x/xpedite520x.c

@@ -36,33 +36,6 @@
 
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
-int checkboard(void)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-	char *s;
-
-	printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	s = getenv("board_rev");
-	if (s)
-		printf("Rev %s, ", s);
-	s = getenv("serial#");
-	if (s)
-		printf("Serial# %s, ", s);
-	s = getenv("board_cfg");
-	if (s)
-		printf("Cfg %s", s);
-	printf("\n");
-
-	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
-	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
-	out_be32(&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
-	out_be32(&ecm->eeer, 0xffffffff);	/* Enable ecm errors */
-
-	return 0;
-}
-
 static void flash_cs_fixup(void)
 {
 	int flash_sel;

board/xes/xpedite5370/xpedite5370.c → board/xes/xpedite537x/xpedite537x.c

@@ -36,26 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
-int checkboard(void)
-{
-	char *s;
-
-	printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	s = getenv("board_rev");
-	if (s)
-		printf("Rev %s, ", s);
-	s = getenv("serial#");
-	if (s)
-		printf("Serial# %s, ", s);
-	s = getenv("board_cfg");
-	if (s)
-		printf("Cfg %s", s);
-	printf("\n");
-
-	return 0;
-}
-
 static void flash_cs_fixup(void)
 {
 	int flash_sel;

board/xes/xpedite550x/Makefile

@@ -0,0 +1,39 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/xes/xpedite550x/ddr.c

@@ -0,0 +1,165 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr3_spd_eeprom_t));
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+/*
+ *     There are traditionally three board-specific SDRAM timing parameters
+ *     which must be calculated based on the particular PCB artwork.  These are:
+ *     1.) CPO (Read Capture Delay)
+ *             - TIMING_CFG_2 register
+ *             Source: Calculation based on board trace lengths and
+ *                     chip-specific internal delays.
+ *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *             - DDR_SDRAM_CLK_CNTL register
+ *             Source: Signal Integrity Simulations
+ *     3.) 2T Timing on Addr/Ctl
+ *             - TIMING_CFG_2 register
+ *             Source: Signal Integrity Simulations
+ *             Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ *     The P2020 processor provides an autoleveling option. Setting CPO to
+ *     0x1f enables this auto configuration.
+ */
+
+typedef struct {
+	unsigned short datarate_mhz_low;
+	unsigned short datarate_mhz_high;
+	unsigned char clk_adjust;
+	unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+		/* Controller 0 */
+                {
+			/* DDR3-600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+                {
+			/* DDR3-800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/*
+	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->twoT_en = 0;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * Enable on-die termination.
+	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
+	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = 3;
+}
+

board/xes/xpedite550x/law.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
+#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
+#endif
+#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/xes/xpedite550x/tlb.c

@@ -0,0 +1,98 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/xes/xpedite550x/xpedite550x.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif

board/xm250/Makefile

@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= xm250.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/xm250/config.mk

@@ -1,35 +0,0 @@
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys XM250 board:
-#
-
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xA3F80000