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@@ -172,396 +172,373 @@
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.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
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.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
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-
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- /*
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- * initialize dram controller registers
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- */
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.globl mem_init
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mem_init:
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- xorw %ax,%ax
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- movl $DBCTL, %edi
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- movb %al, (%edi) /* disable write buffer */
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+ /* Preserve Boot Flags */
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+ movl %ebx, %ebp
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- movl $ECCCTL, %edi
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- movb %al, (%edi) /* disable ECC */
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+ /* initialize dram controller registers */
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+ xorw %ax, %ax
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+ movl $DBCTL, %edi
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+ movb %al, (%edi) /* disable write buffer */
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- movl $DRCTMCTL, %edi
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- movb $0x1E,%al /* Set SDRAM timing for slowest */
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- movb %al, (%edi)
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+ movl $ECCCTL, %edi
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+ movb %al, (%edi) /* disable ECC */
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- /*
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- * setup loop to do 4 external banks starting with bank 3
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- */
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- movl $0xff000000,%eax /* enable last bank and setup */
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- movl $DRCBENDADR, %edi /* ending address register */
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- movl %eax, (%edi)
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+ movl $DRCTMCTL, %edi
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+ movb $0x1e, %al /* Set SDRAM timing for slowest */
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+ movb %al, (%edi)
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- movl $DRCCFG, %edi /* setup */
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- movw $0xbbbb,%ax /* dram config register for */
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- movw %ax, (%edi)
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+ /* setup loop to do 4 external banks starting with bank 3 */
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+ movl $0xff000000, %eax /* enable last bank and setup */
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+ movl $DRCBENDADR, %edi /* ending address register */
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+ movl %eax, (%edi)
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- /*
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- * issue a NOP to all DRAMs
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- */
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- movl $DRCCTL, %edi /* setup DRAM control register with */
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- movb $0x1,%al /* Disable refresh,disable write buffer */
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- movb %al, (%edi)
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- movl $CACHELINESZ, %esi /* just a dummy address to write for */
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- movw %ax, (%esi)
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- /*
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- * delay for 100 usec? 200?
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- * ******this is a cludge for now *************
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- */
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- movw $100,%cx
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-sizdelay:
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- loop sizdelay /* we need 100 usec here */
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- /***********************************************/
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+ movl $DRCCFG, %edi /* setup */
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+ movw $0xbbbb, %ax /* dram config register for */
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+ movw %ax, (%edi)
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- /*
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- * issue all banks precharge
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- */
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- movb $0x2,%al /* All banks precharge */
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- movb %al, (%edi)
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- movw %ax, (%esi)
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+ /* issue a NOP to all DRAMs */
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+ movl $DRCCTL, %edi /* setup DRAM control register with */
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+ movb $0x01, %al /* Disable refresh,disable write buffer */
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+ movb %al, (%edi)
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+ movl $CACHELINESZ, %esi /* just a dummy address to write for */
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+ movw %ax, (%esi)
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- /*
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- * issue 2 auto refreshes to all banks
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- */
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- movb $0x4,%al /* Auto refresh cmd */
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- movb %al, (%edi)
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- movw $2,%cx
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-refresh1:
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- movw %ax, (%esi)
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- loop refresh1
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+ /* delay for 100 usec? */
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+ movw $100, %cx
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+sizdelay:
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+ loop sizdelay
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- /*
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- * issue LOAD MODE REGISTER command
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- */
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- movb $0x3,%al /* Load mode register cmd */
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- movb %al, (%edi)
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- movw %ax, (%esi)
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+ /* issue all banks precharge */
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+ movb $0x02, %al
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+ movb %al, (%edi)
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+ movw %ax, (%esi)
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- /*
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- * issue 8 more auto refreshes to all banks
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- */
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- movb $0x4,%al /* Auto refresh cmd */
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- movb %al, (%edi)
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- movw $8,%cx
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+ /* issue 2 auto refreshes to all banks */
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+ movb $0x04, %al /* Auto refresh cmd */
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+ movb %al, (%edi)
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+ movw $0x02, %cx
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+refresh1:
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+ movw %ax, (%esi)
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+ loop refresh1
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+
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+ /* issue LOAD MODE REGISTER command */
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+ movb $0x03, %al /* Load mode register cmd */
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+ movb %al, (%edi)
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+ movw %ax, (%esi)
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+
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+ /* issue 8 more auto refreshes to all banks */
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+ movb $0x04, %al /* Auto refresh cmd */
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+ movb %al, (%edi)
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+ movw $0x0008, %cx
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refresh2:
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- movw %ax, (%esi)
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- loop refresh2
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+ movw %ax, (%esi)
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+ loop refresh2
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- /*
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- * set control register to NORMAL mode
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- */
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- movb $0x0,%al /* Normal mode value */
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- movb %al, (%edi)
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+ /* set control register to NORMAL mode */
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+ movb $0x00, %al /* Normal mode value */
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+ movb %al, (%edi)
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- /*
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- * size dram starting with external bank 3 moving to external bank 0
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- */
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- movl $0x3,%ecx /* start with external bank 3 */
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+ /*
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+ * size dram starting with external bank 3
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+ * moving to external bank 0
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+ */
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+ movl $0x3, %ecx /* start with external bank 3 */
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nextbank:
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- /*
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- * write col 11 wrap adr
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- */
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- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
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- movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
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- movl %eax, (%esi) /* write max col pattern at max col adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write col 10 wrap adr
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- */
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+ /* write col 11 wrap adr */
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+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
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+ movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
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+ movl %eax, (%esi) /* write max col pattern at max col adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write col 10 wrap adr */
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+ movl $COL10_ADR, %esi /* set address to 10 col wrap address */
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+ movl $COL10_DATA, %eax /* pattern for 10 col wrap */
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+ movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write col 9 wrap adr */
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+ movl $COL09_ADR, %esi /* set address to 9 col wrap address */
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+ movl $COL09_DATA, %eax /* pattern for 9 col wrap */
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+ movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write col 8 wrap adr */
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+ movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
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+ movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
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+ movl %eax, (%esi) /* write min col pattern @ min col adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write row 14 wrap adr */
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+ movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
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+ movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
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+ movl %eax, (%esi) /* write max row pattern at max row adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write row 13 wrap adr */
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+ movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
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+ movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
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+ movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write row 12 wrap adr */
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+ movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
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+ movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
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+ movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
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+ movl (%esi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /* write row 11 wrap adr */
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+ movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
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+ movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
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+ movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
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+ movl (%edi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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- movl $COL10_ADR, %esi /* set address to 10 col wrap address */
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- movl $COL10_DATA, %eax /* pattern for 10 col wrap */
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- movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write col 9 wrap adr
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- */
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- movl $COL09_ADR, %esi /* set address to 9 col wrap address */
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- movl $COL09_DATA, %eax /* pattern for 9 col wrap */
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- movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write col 8 wrap adr
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- */
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- movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
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- movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
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- movl %eax, (%esi) /* write min col pattern @ min col adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write row 14 wrap adr
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- */
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- movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
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- movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
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- movl %eax, (%esi) /* write max row pattern at max row adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write row 13 wrap adr
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- */
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- movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
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- movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
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- movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write row 12 wrap adr
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- */
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- movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
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- movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
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- movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
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- movl (%esi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write row 11 wrap adr
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- */
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- movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
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- movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
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- movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
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- movl (%edi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * write row 10 wrap adr --- this write is really to determine number of banks
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- */
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- movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
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- movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
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- movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
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- movl (%edi), %ebx /* optional read */
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- cmpl %ebx,%eax /* to verify write */
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- jnz bad_ram /* this ram is bad */
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- /*
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- * read data @ row 12 wrap adr to determine * banks,
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- * and read data @ row 14 wrap adr to determine * rows.
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- * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
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- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
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- * if data @ row 12 wrap == 11 or 12, we have 4 banks,
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- */
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- xorw %di,%di /* value for 2 banks in DI */
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- movl (%esi), %ebx /* read from 12 row wrap to check banks
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- * (esi is setup from the write to row 12 wrap) */
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- cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
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- jz only2 /* if pattern == AA, we only have 2 banks */
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+ /*
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+ * write row 10 wrap adr --- this write is really to determine
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+ * number of banks
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+ */
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+ movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
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+ movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
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+ movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
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+ movl (%edi), %ebx /* optional read */
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+ cmpl %ebx, %eax /* to verify write */
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+ jnz bad_ram /* this ram is bad */
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+
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+ /*
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+ * read data @ row 12 wrap adr to determine * banks,
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+ * and read data @ row 14 wrap adr to determine * rows.
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+ * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
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+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
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+ * if data @ row 12 wrap == 11 or 12, we have 4 banks,
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+ */
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+ xorw %di, %di /* value for 2 banks in DI */
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+ movl (%esi), %ebx /* read from 12 row wrap to check banks */
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+ /* (esi is setup from the write to row 12 wrap) */
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+ cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
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+ jz only2 /* if pattern == AA, we only have 2 banks */
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/* 4 banks */
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- movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
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- cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
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- jz only2
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- cmpl $ROW12_DATA, %ebx /* and 12 */
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- jnz bad_ram /* its bad if not 11 or 12! */
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+ movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
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+ cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
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+ jz only2
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+ cmpl $ROW12_DATA, %ebx /* and 12 */
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+ jnz bad_ram /* its bad if not 11 or 12! */
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/* fall through */
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only2:
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/*
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* validate row mask
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*/
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- movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
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- movl (%esi), %eax /* read actual number of rows @ row14 adr */
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+ movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
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+ movl (%esi), %eax /* read actual number of rows @ row14 adr */
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- cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
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- jb bad_ram
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+ cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
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+ jb bad_ram
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- cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
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- ja bad_ram
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+ cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
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+ ja bad_ram
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+
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+ cmpb %ah, %al /* verify all 4 bytes of dword same */
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+ jnz bad_ram
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+ movl %eax, %ebx
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+ shrl $16, %ebx
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+ cmpw %bx, %ax
|
|
|
+ jnz bad_ram
|
|
|
+
|
|
|
+ /*
|
|
|
+ * read col 11 wrap adr for real column data value
|
|
|
+ */
|
|
|
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
|
|
|
+ movl (%esi), %eax /* read real col number at max col adr */
|
|
|
+
|
|
|
+ /*
|
|
|
+ * validate column data
|
|
|
+ */
|
|
|
+ cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
|
|
|
+ jb bad_ram
|
|
|
+
|
|
|
+ cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
|
|
|
+ ja bad_ram
|
|
|
+
|
|
|
+ subl $COL08_DATA, %eax /* normalize column data to zero */
|
|
|
+ jc bad_ram
|
|
|
+ cmpb %ah, %al /* verify all 4 bytes of dword equal */
|
|
|
+ jnz bad_ram
|
|
|
+ movl %eax, %edx
|
|
|
+ shrl $16, %edx
|
|
|
+ cmpw %dx, %ax
|
|
|
+ jnz bad_ram
|
|
|
+
|
|
|
+ /*
|
|
|
+ * merge bank and col data together
|
|
|
+ */
|
|
|
+ addw %di, %dx /* merge of bank and col info in dl */
|
|
|
+
|
|
|
+ /*
|
|
|
+ * fix ending addr mask based upon col info
|
|
|
+ */
|
|
|
+ movb $0x03, %al
|
|
|
+ subb %dh, %al /* dh contains the overflow from the bank/col merge */
|
|
|
+ movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
|
|
|
+ xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
|
|
|
+ shrb %cl, %dh
|
|
|
+ incb %dh /* ending addr is 1 greater than real end */
|
|
|
+ xchgw %cx, %ax /* cx is bank number again */
|
|
|
|
|
|
- cmpb %ah,%al /* verify all 4 bytes of dword same */
|
|
|
- jnz bad_ram
|
|
|
- movl %eax,%ebx
|
|
|
- shrl $16,%ebx
|
|
|
- cmpw %bx,%ax
|
|
|
- jnz bad_ram
|
|
|
- /*
|
|
|
- * read col 11 wrap adr for real column data value
|
|
|
- */
|
|
|
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
|
|
|
- movl (%esi), %eax /* read real col number at max col adr */
|
|
|
- /*
|
|
|
- * validate column data
|
|
|
- */
|
|
|
- cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
|
|
|
- jb bad_ram
|
|
|
-
|
|
|
- cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
|
|
|
- ja bad_ram
|
|
|
-
|
|
|
- subl $COL08_DATA, %eax /* normalize column data to zero */
|
|
|
- jc bad_ram
|
|
|
- cmpb %ah,%al /* verify all 4 bytes of dword equal */
|
|
|
- jnz bad_ram
|
|
|
- movl %eax,%edx
|
|
|
- shrl $16,%edx
|
|
|
- cmpw %dx,%ax
|
|
|
- jnz bad_ram
|
|
|
- /*
|
|
|
- * merge bank and col data together
|
|
|
- */
|
|
|
- addw %di,%dx /* merge of bank and col info in dl */
|
|
|
- /*
|
|
|
- * fix ending addr mask based upon col info
|
|
|
- */
|
|
|
- movb $3,%al
|
|
|
- subb %dh,%al /* dh contains the overflow from the bank/col merge */
|
|
|
- movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
|
|
|
- xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
|
|
|
- shrb %cl,%dh /* */
|
|
|
- incb %dh /* ending addr is 1 greater than real end */
|
|
|
- xchgw %cx,%ax /* cx is bank number again */
|
|
|
- /*
|
|
|
- * issue all banks precharge
|
|
|
- */
|
|
|
bad_reint:
|
|
|
- movl $DRCCTL, %esi /* setup DRAM control register with */
|
|
|
- movb $0x2,%al /* All banks precharge */
|
|
|
- movb %al, (%esi)
|
|
|
- movl $CACHELINESZ, %esi /* address to init read buffer */
|
|
|
- movw %ax, (%esi)
|
|
|
+ /*
|
|
|
+ * issue all banks precharge
|
|
|
+ */
|
|
|
+ movl $DRCCTL, %esi /* setup DRAM control register with */
|
|
|
+ movb $0x02, %al /* All banks precharge */
|
|
|
+ movb %al, (%esi)
|
|
|
+ movl $CACHELINESZ, %esi /* address to init read buffer */
|
|
|
+ movw %ax, (%esi)
|
|
|
|
|
|
- /*
|
|
|
- * update ENDING ADDRESS REGISTER
|
|
|
- */
|
|
|
- movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
- movl %ecx,%ebx
|
|
|
+ /*
|
|
|
+ * update ENDING ADDRESS REGISTER
|
|
|
+ */
|
|
|
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
+ movl %ecx, %ebx
|
|
|
addl %ebx, %edi
|
|
|
- movb %dh, (%edi)
|
|
|
- /*
|
|
|
- * update CONFIG REGISTER
|
|
|
- */
|
|
|
- xorb %dh,%dh
|
|
|
- movw $0x00f,%bx
|
|
|
- movw %cx,%ax
|
|
|
- shlw $2,%ax
|
|
|
- xchgw %cx,%ax
|
|
|
- shlw %cl,%dx
|
|
|
- shlw %cl,%bx
|
|
|
- notw %bx
|
|
|
- xchgw %cx,%ax
|
|
|
- movl $DRCCFG, %edi
|
|
|
- mov (%edi), %ax
|
|
|
- andw %bx,%ax
|
|
|
- orw %dx,%ax
|
|
|
- movw %ax, (%edi)
|
|
|
- jcxz cleanup
|
|
|
-
|
|
|
- decw %cx
|
|
|
- movl %ecx,%ebx
|
|
|
- movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
- movb $0xff,%al
|
|
|
+ movb %dh, (%edi)
|
|
|
+
|
|
|
+ /*
|
|
|
+ * update CONFIG REGISTER
|
|
|
+ */
|
|
|
+ xorb %dh, %dh
|
|
|
+ movw $0x000f, %bx
|
|
|
+ movw %cx, %ax
|
|
|
+ shlw $2, %ax
|
|
|
+ xchgw %cx, %ax
|
|
|
+ shlw %cl, %dx
|
|
|
+ shlw %cl, %bx
|
|
|
+ notw %bx
|
|
|
+ xchgw %cx, %ax
|
|
|
+ movl $DRCCFG, %edi
|
|
|
+ movw (%edi), %ax
|
|
|
+ andw %bx, %ax
|
|
|
+ orw %dx, %ax
|
|
|
+ movw %ax, (%edi)
|
|
|
+ jcxz cleanup
|
|
|
+
|
|
|
+ decw %cx
|
|
|
+ movl %ecx, %ebx
|
|
|
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
+ movb $0xff, %al
|
|
|
addl %ebx, %edi
|
|
|
- movb %al, (%edi)
|
|
|
- /*
|
|
|
- * set control register to NORMAL mode
|
|
|
- */
|
|
|
- movl $DRCCTL, %esi /* setup DRAM control register with */
|
|
|
- movb $0x0,%al /* Normal mode value */
|
|
|
- movb %al, (%esi)
|
|
|
- movl $CACHELINESZ, %esi /* address to init read buffer */
|
|
|
- movw %ax, (%esi)
|
|
|
- jmp nextbank
|
|
|
+ movb %al, (%edi)
|
|
|
+
|
|
|
+ /*
|
|
|
+ * set control register to NORMAL mode
|
|
|
+ */
|
|
|
+ movl $DRCCTL, %esi /* setup DRAM control register with */
|
|
|
+ movb $0x00, %al /* Normal mode value */
|
|
|
+ movb %al, (%esi)
|
|
|
+ movl $CACHELINESZ, %esi /* address to init read buffer */
|
|
|
+ movw %ax, (%esi)
|
|
|
+ jmp nextbank
|
|
|
|
|
|
cleanup:
|
|
|
- movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
- movw $4,%cx
|
|
|
- xorw %ax,%ax
|
|
|
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
+ movw $0x04, %cx
|
|
|
+ xorw %ax, %ax
|
|
|
cleanuplp:
|
|
|
- movb (%edi), %al
|
|
|
- orb %al,%al
|
|
|
- jz emptybank
|
|
|
+ movb (%edi), %al
|
|
|
+ orb %al, %al
|
|
|
+ jz emptybank
|
|
|
|
|
|
- addb %ah,%al
|
|
|
- jns nottoomuch
|
|
|
+ addb %ah, %al
|
|
|
+ jns nottoomuch
|
|
|
|
|
|
- movb $0x7f,%al
|
|
|
+ movb $0x7f, %al
|
|
|
nottoomuch:
|
|
|
- movb %al,%ah
|
|
|
- orb $0x80,%al
|
|
|
- movb %al, (%edi)
|
|
|
+ movb %al, %ah
|
|
|
+ orb $0x80, %al
|
|
|
+ movb %al, (%edi)
|
|
|
emptybank:
|
|
|
- incl %edi
|
|
|
- loop cleanuplp
|
|
|
+ incl %edi
|
|
|
+ loop cleanuplp
|
|
|
|
|
|
#if defined CONFIG_SYS_SDRAM_DRCTMCTL
|
|
|
/* just have your hardware desinger _GIVE_ you what you need here! */
|
|
|
- movl $DRCTMCTL, %edi
|
|
|
- movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
|
|
|
- movb %al, (%edi)
|
|
|
+ movl $DRCTMCTL, %edi
|
|
|
+ movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
|
|
|
+ movb %al, (%edi)
|
|
|
#else
|
|
|
#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
|
|
|
- /* set the CAS latency now since it is hard to do
|
|
|
- * when we run from the RAM */
|
|
|
- movl $DRCTMCTL, %edi /* DRAM timing register */
|
|
|
- movb (%edi), %al
|
|
|
+ /*
|
|
|
+ * Set the CAS latency now since it is hard to do
|
|
|
+ * when we run from the RAM
|
|
|
+ */
|
|
|
+ movl $DRCTMCTL, %edi /* DRAM timing register */
|
|
|
+ movb (%edi), %al
|
|
|
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
|
|
|
- andb $0xef, %al
|
|
|
+ andb $0xef, %al
|
|
|
#endif
|
|
|
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
|
|
|
- orb $0x10, %al
|
|
|
+ orb $0x10, %al
|
|
|
#endif
|
|
|
- movb %al, (%edi)
|
|
|
+ movb %al, (%edi)
|
|
|
#endif
|
|
|
#endif
|
|
|
- movl $DRCCTL, %edi /* DRAM Control register */
|
|
|
- movb $0x3,%al /* Load mode register cmd */
|
|
|
- movb %al, (%edi)
|
|
|
- movw %ax, (%esi)
|
|
|
+ movl $DRCCTL, %edi /* DRAM Control register */
|
|
|
+ movb $0x03, %al /* Load mode register cmd */
|
|
|
+ movb %al, (%edi)
|
|
|
+ movw %ax, (%esi)
|
|
|
|
|
|
|
|
|
- movl $DRCCTL, %edi /* DRAM Control register */
|
|
|
- movb $0x18,%al /* Enable refresh and NORMAL mode */
|
|
|
- movb %al, (%edi)
|
|
|
+ movl $DRCCTL, %edi /* DRAM Control register */
|
|
|
+ movb $0x18, %al /* Enable refresh and NORMAL mode */
|
|
|
+ movb %al, (%edi)
|
|
|
|
|
|
- jmp dram_done
|
|
|
+ jmp dram_done
|
|
|
|
|
|
bad_ram:
|
|
|
- xorl %edx,%edx
|
|
|
- xorl %edi,%edi
|
|
|
- jmp bad_reint
|
|
|
+ xorl %edx, %edx
|
|
|
+ xorl %edi, %edi
|
|
|
+ jmp bad_reint
|
|
|
|
|
|
dram_done:
|
|
|
+ /* Restore Boot Flags */
|
|
|
+ movl %ebx, %ebp
|
|
|
+ jmp mem_init_ret
|
|
|
|
|
|
#if CONFIG_SYS_SDRAM_ECC_ENABLE
|
|
|
- /*
|
|
|
- * We are in the middle of an existing 'call' - Need to store the
|
|
|
- * existing return address before making another 'call'
|
|
|
- */
|
|
|
- movl %ebp, %ebx
|
|
|
-
|
|
|
- /* Get the memory size */
|
|
|
- movl $init_ecc, %ebp
|
|
|
- jmpl get_mem_size
|
|
|
-
|
|
|
+.globl init_ecc
|
|
|
init_ecc:
|
|
|
- /* Restore the orignal return address */
|
|
|
- movl %ebx, %ebp
|
|
|
-
|
|
|
/* A nominal memory test: just a byte at each address line */
|
|
|
- movl %eax, %ecx
|
|
|
- shrl $0x1, %ecx
|
|
|
+ movl %eax, %ecx
|
|
|
+ shrl $0x1, %ecx
|
|
|
movl $0x1, %edi
|
|
|
memtest0:
|
|
|
movb $0xa5, (%edi)
|
|
|
- cmpb $0xa5, (%edi)
|
|
|
+ cmpb $0xa5, (%edi)
|
|
|
jne out
|
|
|
- shrl $1, %ecx
|
|
|
- andl %ecx,%ecx
|
|
|
+ shrl $0x1, %ecx
|
|
|
+ andl %ecx, %ecx
|
|
|
jz set_ecc
|
|
|
- shll $1, %edi
|
|
|
+ shll $0x1, %edi
|
|
|
jmp memtest0
|
|
|
|
|
|
set_ecc:
|
|
|
@@ -570,25 +547,28 @@ set_ecc:
|
|
|
xorl %esi, %esi
|
|
|
xorl %edi, %edi
|
|
|
xorl %eax, %eax
|
|
|
- shrl $2, %ecx
|
|
|
+ shrl $0x2, %ecx
|
|
|
cld
|
|
|
rep stosl
|
|
|
- /* enable read, write buffers */
|
|
|
- movb $0x11, %al
|
|
|
- movl $DBCTL, %edi
|
|
|
- movb %al, (%edi)
|
|
|
- /* enable NMI mapping for ECC */
|
|
|
- movl $ECCINT, %edi
|
|
|
- mov $0x10, %al
|
|
|
- movb %al, (%edi)
|
|
|
- /* Turn on ECC */
|
|
|
- movl $ECCCTL, %edi
|
|
|
- mov $0x05, %al
|
|
|
- movb %al, (%edi)
|
|
|
-#endif
|
|
|
+
|
|
|
+ /* enable read, write buffers */
|
|
|
+ movb $0x11, %al
|
|
|
+ movl $DBCTL, %edi
|
|
|
+ movb %al, (%edi)
|
|
|
+
|
|
|
+ /* enable NMI mapping for ECC */
|
|
|
+ movl $ECCINT, %edi
|
|
|
+ movb $0x10, %al
|
|
|
+ movb %al, (%edi)
|
|
|
+
|
|
|
+ /* Turn on ECC */
|
|
|
+ movl $ECCCTL, %edi
|
|
|
+ movb $0x05, %al
|
|
|
+ movb %al,(%edi)
|
|
|
|
|
|
out:
|
|
|
- jmp *%ebp
|
|
|
+ jmp init_ecc_ret
|
|
|
+#endif
|
|
|
|
|
|
/*
|
|
|
* Read and decode the sc520 DRCBENDADR MMCR and return the number of
|
|
|
@@ -596,7 +576,7 @@ out:
|
|
|
*/
|
|
|
.globl get_mem_size
|
|
|
get_mem_size:
|
|
|
- movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
|
|
|
|
|
|
bank0: movl (%edi), %eax
|
|
|
movl %eax, %ecx
|
|
|
@@ -604,7 +584,7 @@ bank0: movl (%edi), %eax
|
|
|
jz bank1
|
|
|
andl $0x0000007f, %eax
|
|
|
shll $22, %eax
|
|
|
- movl %eax, %ebx
|
|
|
+ movl %eax, %edx
|
|
|
|
|
|
bank1: movl (%edi), %eax
|
|
|
movl %eax, %ecx
|
|
|
@@ -612,7 +592,7 @@ bank1: movl (%edi), %eax
|
|
|
jz bank2
|
|
|
andl $0x00007f00, %eax
|
|
|
shll $14, %eax
|
|
|
- movl %eax, %ebx
|
|
|
+ movl %eax, %edx
|
|
|
|
|
|
bank2: movl (%edi), %eax
|
|
|
movl %eax, %ecx
|
|
|
@@ -620,7 +600,7 @@ bank2: movl (%edi), %eax
|
|
|
jz bank3
|
|
|
andl $0x007f0000, %eax
|
|
|
shll $6, %eax
|
|
|
- movl %eax, %ebx
|
|
|
+ movl %eax, %edx
|
|
|
|
|
|
bank3: movl (%edi), %eax
|
|
|
movl %eax, %ecx
|
|
|
@@ -628,8 +608,8 @@ bank3: movl (%edi), %eax
|
|
|
jz done
|
|
|
andl $0x7f000000, %eax
|
|
|
shrl $2, %eax
|
|
|
- movl %eax, %ebx
|
|
|
+ movl %eax, %edx
|
|
|
|
|
|
done:
|
|
|
- movl %ebx, %eax
|
|
|
- jmp *%ebp
|
|
|
+ movl %edx, %eax
|
|
|
+ jmp get_mem_size_ret
|
Wolfgang Denk