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@@ -1,5 +1,5 @@
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/*
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- * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
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+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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@@ -166,12 +166,14 @@ int checkcpu (void)
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}
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#endif
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+#if defined(CONFIG_FSL_LBC)
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if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freqLocalBus);
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}
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+#endif
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#ifdef CONFIG_CPM2
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printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
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@@ -284,7 +286,10 @@ void mpc85xx_reginfo(void)
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{
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print_tlbcam();
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print_laws();
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+#if defined(CONFIG_FSL_LBC)
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print_lbc_regs();
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+#endif
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+
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}
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/* Common ddr init for non-corenet fsl 85xx platforms */
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@@ -330,8 +335,10 @@ phys_size_t initdram(int board_type)
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ddr_enable_ecc(dram_size);
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#endif
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+#if defined(CONFIG_FSL_LBC)
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/* Some boards also have sdram on the lbc */
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lbc_sdram_init();
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+#endif
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puts("DDR: ");
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return dram_size;
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