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@@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id)
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out:
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return pll_out;
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}
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+
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+int set_cpu_clk_info(void)
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+{
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+ gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
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+ /* DDR PHY uses an x2 input clock */
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+ gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
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+ (clk_get(DAVINCI_DDR_CLKID) / 1000000);
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+ gd->bd->bi_dsp_freq = 0;
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+ return 0;
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+}
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+
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#else /* CONFIG_SOC_DA8XX */
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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@@ -187,17 +198,9 @@ unsigned int davinci_clk_get(unsigned int div)
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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}
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#endif
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-#endif /* !CONFIG_SOC_DA8XX */
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int set_cpu_clk_info(void)
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{
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-#ifdef CONFIG_SOC_DA8XX
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- gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
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- /* DDR PHY uses an x2 input clock */
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- gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
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- (clk_get(DAVINCI_DDR_CLKID) / 1000000);
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-#else
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-
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unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
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#if defined(CONFIG_SOC_DM365)
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pllbase = DAVINCI_PLL_CNTRL1_BASE;
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@@ -216,10 +219,12 @@ int set_cpu_clk_info(void)
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pllbase = DAVINCI_PLL_CNTRL0_BASE;
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#endif
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gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
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-#endif
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+
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return 0;
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}
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+#endif /* !CONFIG_SOC_DA8XX */
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+
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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