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@@ -31,7 +31,6 @@
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_CM5200 1 /* ... on CM5200 platform */
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#define CONFIG_CM5200 1 /* ... on CM5200 platform */
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-
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/*
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/*
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* Supported commands
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* Supported commands
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*/
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*/
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@@ -60,7 +59,6 @@
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
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#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
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-
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/*
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/*
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* Ethernet configuration
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* Ethernet configuration
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*/
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*/
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@@ -71,7 +69,6 @@
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
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#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
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-
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/*
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/*
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* POST support
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* POST support
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*/
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*/
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@@ -80,11 +77,9 @@
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/* List of I2C addresses to be verified by POST */
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/* List of I2C addresses to be verified by POST */
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#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
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#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
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-
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/* display image timestamps */
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/* display image timestamps */
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#define CONFIG_TIMESTAMP 1
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#define CONFIG_TIMESTAMP 1
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-
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/*
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/*
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* Autobooting
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* Autobooting
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*/
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*/
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@@ -137,19 +132,16 @@
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""
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""
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#define CONFIG_BOOTCOMMAND "run flash_flash"
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#define CONFIG_BOOTCOMMAND "run flash_flash"
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-
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/*
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/*
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* Low level configuration
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* Low level configuration
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*/
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*/
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-
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/*
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/*
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* Clock configuration
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* Clock configuration
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*/
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*/
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#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
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#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
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#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
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#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
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-
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/*
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/*
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* Memory map
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* Memory map
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*/
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*/
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@@ -184,7 +176,7 @@
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*/
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*/
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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#define CFG_FLASH_CFI_DRIVER 1
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-#define CFG_FLASH_BASE 0xfc000000
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+#define CFG_FLASH_BASE 0xfc000000
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/* we need these despite using CFI */
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/* we need these despite using CFI */
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
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#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
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@@ -215,7 +207,6 @@
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x00000001
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#define CFG_CS_DEADCYCLE 0x00000001
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-
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/*
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/*
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* SDRAM configuration
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* SDRAM configuration
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* settings for k4s561632E-xx75, assuming XLB = 132 MHz
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* settings for k4s561632E-xx75, assuming XLB = 132 MHz
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@@ -225,8 +216,6 @@
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#define SDRAM_CONFIG1 0xE2333900
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#define SDRAM_CONFIG1 0xE2333900
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#define SDRAM_CONFIG2 0x8EE70000
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#define SDRAM_CONFIG2 0x8EE70000
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-
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-
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/*
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/*
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* MTD configuration
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* MTD configuration
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*/
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*/
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@@ -238,7 +227,6 @@
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"2m(kernel),27904k(rootfs)," \
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"2m(kernel),27904k(rootfs)," \
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"-(config)"
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"-(config)"
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-
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/*
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/*
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* I2C configuration
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* I2C configuration
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*/
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*/
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@@ -249,13 +237,11 @@
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#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
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#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
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#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */
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#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */
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-
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/*
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/*
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* RTC configuration
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* RTC configuration
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*/
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*/
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#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
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#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
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-
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/*
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/*
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* USB configuration
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* USB configuration
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*/
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*/
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@@ -284,7 +270,6 @@
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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-
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/*
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/*
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* Pin multiplexing configuration
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* Pin multiplexing configuration
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*/
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*/
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@@ -302,7 +287,6 @@
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*/
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*/
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#define CFG_GPS_PORT_CONFIG 0x10559C44
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#define CFG_GPS_PORT_CONFIG 0x10559C44
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-
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/*
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/*
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* Miscellaneous configurable options
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* Miscellaneous configurable options
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*/
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*/
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@@ -322,7 +306,6 @@
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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-
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/*
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/*
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* Various low-level settings
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* Various low-level settings
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*/
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*/
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@@ -334,7 +317,6 @@
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#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */
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#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */
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-
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/*
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/*
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* Cache Configuration
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* Cache Configuration
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*/
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*/
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@@ -343,7 +325,6 @@
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#endif
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-
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/*
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/*
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* Flat Device Tree support
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* Flat Device Tree support
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*/
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*/
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