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@@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs)
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/* Clear MCSR */
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/* Clear MCSR */
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mtspr(SPRN_MCSR, val);
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mtspr(SPRN_MCSR, val);
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}
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}
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+
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+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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+ /*
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+ * Read and print ECC status register/info:
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+ * The faulting address is only known upon uncorrectable ECC
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+ * errors.
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+ */
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+ mfsdram(SDRAM_ECCES, val);
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+ if (val & SDRAM_ECCES_CE)
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+ printf("ECC: Correctable error\n");
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+ if (val & SDRAM_ECCES_UE) {
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+ printf("ECC: Uncorrectable error at 0x%02x%08x\n",
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+ mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
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+ }
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+#endif /* CONFIG_DDR_ECC ... */
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+
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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mfsdram(DDR0_00, val) ;
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mfsdram(DDR0_00, val) ;
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printf("DDR0: DDR0_00 %lx\n", val);
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printf("DDR0: DDR0_00 %lx\n", val);
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