Merge branch 'next' of git://git.denx.de/u-boot-pxa into next

arch/arm/include/asm/arch-pxa/pxa-regs.h

@@ -992,10 +992,6 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE		__REG(0x4C000068)
 #define UHCHIT		__REG(0x4C00006C)
 
-#if defined(CONFIG_CPU_MONAHANS)
-#define UP2OCR		__REG(0x40600020)
-#endif
-
 #define UHCHR_FSBIR	(1<<0)
 #define UHCHR_FHR	(1<<1)
 #define UHCHR_CGR	(1<<2)
@@ -1015,6 +1011,24 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE_HBAIE	(1<<8)
 #define UHCHIE_RWIE	(1<<7)
 
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+#define UP2OCR		__REG(0x40600020)
+#endif
+
+#define UP2OCR_HXOE	(1<<17)
+#define UP2OCR_HXS	(1<<16)
+#define UP2OCR_IDON	(1<<10)
+#define UP2OCR_EXSUS	(1<<9)
+#define UP2OCR_EXSP	(1<<8)
+#define UP2OCR_DMSTATE	(1<<7)
+#define UP2OCR_VPM	(1<<6)
+#define UP2OCR_DPSTATE	(1<<5)
+#define UP2OCR_DPPUE	(1<<4)
+#define UP2OCR_DMPDE	(1<<3)
+#define UP2OCR_DPPDE	(1<<2)
+#define UP2OCR_CPVPE	(1<<1)
+#define UP2OCR_CPVEN	(1<<0)
+
 #endif
 
 /*
@@ -2407,6 +2421,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
 #define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
 
+#define MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
+#define MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
+#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */

drivers/mmc/pxa_mmc.c

@@ -126,7 +126,7 @@ mmc_block_read(uchar * dst, ulong src, ulong len)
 	MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
 	while (len) {
 		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
-#ifdef CONFIG_PXA27X
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 			int i;
 			for (i = min(len, 32); i; i--) {
 				*dst++ = *((volatile uchar *)&MMC_RXFIFO);
@@ -558,8 +558,11 @@ mmc_legacy_init(int verbose)
 	set_GPIO_mode(GPIO6_MMCCLK_MD);
 	set_GPIO_mode(GPIO8_MMCCS0_MD);
 #endif
+#ifdef CONFIG_CPU_MONAHANS	/* pxa3xx */
+	CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1;
+#else	/* pxa2xx */
 	CKEN |= CKEN12_MMC;	/* enable MMC unit clock */
-
+#endif
 	MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
 	MMC_RESTO = MMC_RES_TO_MAX;
 	MMC_SPI = MMC_SPI_DISABLE;
@@ -584,11 +587,7 @@ mmc_legacy_init(int verbose)
 			debug("Detected SD card\n");
 			break;
 		}
-#ifdef CONFIG_PXA27X
-		udelay(10000);
-#else
 		udelay(200000);
-#endif
 	}
 
 	if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) {
@@ -598,11 +597,7 @@ mmc_legacy_init(int verbose)
 
 		retries = 10;
 		while (retries-- && resp && !(resp[0] & 0x80000000)) {
-#ifdef CONFIG_PXA27X
-			udelay(10000);
-#else
 			udelay(200000);
-#endif
 			resp =
 			    mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000,
 				    MMC_CMDAT_R3);
@@ -632,7 +627,7 @@ mmc_legacy_init(int verbose)
 	MMC_CLKRT = 0;		/* 20 MHz */
 	resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
 
-#ifdef CONFIG_PXA27X
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	if (IF_TYPE_SD == mmc_dev.if_type) {
 		resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1);
 		resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1);