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@@ -214,14 +214,14 @@
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#define mem_dlycal 0x0084 /* delay line calibration register */
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#define mem_eccesr 0x0098 /* ECC error status */
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-#ifdef CONFIG_440_GX
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+#ifdef CONFIG_440GX
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#define sdr_amp 0x0240
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#define sdr_xpllc 0x01c1
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#define sdr_xplld 0x01c2
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#define sdr_xcr 0x01c0
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#define sdr_sdstp2 0x4001
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#define sdr_sdstp3 0x4003
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-#endif /* CONFIG_440_GX */
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+#endif /* CONFIG_440GX */
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#ifdef CONFIG_440SPE
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#undef sdr_sdstp2
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@@ -759,9 +759,6 @@
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#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
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#endif /* CONFIG_440SPE */
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-#ifndef CONFIG_440_GX
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-#endif /* not CONFIG_440SPE */
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-
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/*-----------------------------------------------------------------------------
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| External Bus Controller
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+----------------------------------------------------------------------------*/
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@@ -1626,7 +1623,7 @@
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#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
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UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
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-#endif /* CONFIG_440_GX */
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+#endif /* CONFIG_440GX */
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/*---------------------------------------------------------------------------+
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| Universal interrupt controller interrupts
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+---------------------------------------------------------------------------*/
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