Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2

CHANGELOG

@@ -1,3 +1,687 @@
+commit 467bcee11fe26ad422f2de971aa70866079870f2
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Fri Dec 14 15:36:18 2007 +0100
+
+    cfi_flash: Add manufacturer-specific fixups
+
+    Run fixups based on the JEDEC manufacturer ID independent of the
+    command set ID.
+
+    This changes current behaviour: Previously, geometry reversal for AMD
+    chips were done based on the command set ID, while they are now done
+    based on the JEDEC manufacturer and device ID.
+
+    Also add fixup for top-boot Atmel chips. A fixup is needed for
+    AT49BV6416(T) too, but since u-boot currently only reads the low byte
+    of the device ID, there's no way to tell it apart from AT49BV642D,
+    which should not have this fixup. Since AT49BV642D support is
+    necessary to get ATNGW100 board support into mainline, I've commented
+    out the fixup for now.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 0ddf06ddf6b4bd057ad4c5f0dffea7870ba06a2a
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Fri Dec 14 15:36:17 2007 +0100
+
+    cfi_flash: Add cmdset-specific init functions
+
+    Move things like reading JEDEC IDs and fixing up geometry reversal
+    into separate functions. The geometry reversal fixup is now performed
+    by altering the qry structure directly, which makes the sector init
+    code slightly cleaner.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit e23741f4a6d8047520ef0d4971762749b3587d32
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Fri Dec 14 15:36:16 2007 +0100
+
+    cfi_flash: Read whole QRY structure in one go
+
+    Read out the whole CFI Standard Query structure after successful cfi
+    identification. This allows subsequent code to access this information
+    directly without having to go through flash_read_uchar() and friends.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit df9c25ea04b38a0e05d4f8c73c5cc144cdafa7db
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Mon Dec 17 11:02:44 2007 +0100
+
+    AVR32: Fix logic inversion in disable_interrupts()
+
+    disable_interrupts() should return nonzero if interrupts were
+    _enabled_ before, not disabled.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit acac475212cbedb17b321a363a1c878e2b47b37f
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Fri Dec 14 16:51:22 2007 +0100
+
+    AVR32: Enable interrupts at bootup
+
+    The timer code depends on the timer interrupt to keep track of the
+    upper 32 bits of the cycle counter. This obviously doesn't work when
+    interrupts are disabled the whole time.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 9570bcd87f4db255514f43b6701746c412f8fef0
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Nov 15 10:03:45 2007 +0100
+
+    AVR32: Fix wrong pin setup for USART3
+
+    As reported by Gerhard Berghofer:
+
+    in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
+    instead of PB18 and PB19.
+
+    which is obviously correct. There's currently no code that uses
+    USART3, but custom boards may run into problems.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 09ea0de03dcc3ee7af045b0b572227bda2c1c918
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Nov 1 12:44:20 2007 +0100
+
+    README: Remove ATSTK1000 daughterboard list
+
+    As noted by Kim Phillips, these lists tend to become out of date.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit c81cbbad21cb0ae983e2e796211202234cdc8be2
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Tue Oct 30 14:56:36 2007 +0100
+
+    Add ATSTK100[234] to MAINTAINERS
+
+    Add all the ATSTK1000 daughterboards to MAINTAINERS along with their
+    "mother". Also update the entry for ATSTK1000 to be not only about the
+    AP7000 CPU; it's intended to handle all CPUs in the AT32AP family.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 64ff2357b1727213803591813dbc779c924bf772
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Mon Oct 29 13:02:54 2007 +0100
+
+    AVR32: Add support for the ATSTK1004 board
+
+    ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU,
+    which is a derivative of AT32AP7000.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 667568db157f374b85abd7e03596ddd1f0b25681
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Mon Oct 29 13:02:54 2007 +0100
+
+    AVR32: Add support for the ATSTK1003 board
+
+    ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU,
+    which is a derivative of AT32AP7000.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 5fee84a794a51ec830548cda485a770efb018b92
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Mon Oct 29 13:23:33 2007 +0100
+
+    AVR32: Make some AT32AP700x peripherals optional
+
+    Add a chip-features file providing definitions of the form
+
+    AT32AP700x_CHIP_HAS_<peripheral>
+
+    to indicate the availability of the given peripheral on the currently
+    selected chip.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 36f28f8a9605ee5dcfa330482cfc62171261af97
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Mon Oct 29 13:09:56 2007 +0100
+
+    AVR32: Rename at32ap7000 -> at32ap700x
+
+    The SoC-specific code for all the AT32AP700x CPUs is practically
+    identical; the only difference is that some chips have less features
+    than others. By doing this rename, we can add support for the AP7000
+    derivatives simply by making some features conditional.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Fri Jun 29 18:22:34 2007 +0200
+
+    atmel_mci: Show SR when block read fails
+
+    Show controller status as well as card status when an error occurs
+    during block read.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 12d30aa79779c2aa7a998bbae4c075f822a53004
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Dec 13 12:56:34 2007 +0100
+
+    cfi_flash: Use map_physmem() and unmap_physmem()
+
+    Use map_physmem() and unmap_physmem() to convert from physical to
+    virtual addresses. This gives the arch a chance to provide an uncached
+    mapping for flash accesses.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 4d7d6936eb29af7cca330937808312aa5f61454d
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Dec 13 12:56:33 2007 +0100
+
+    Introduce map_physmem() and unmap_physmem()
+
+    map_physmem() returns a virtual address which can be used to access a
+    given physical address without involving the cache. unmap_physmem()
+    should be called when the virtual address returned by map_physmem() is
+    no longer needed.
+
+    This patch adds a stub implementation which simply returns the
+    physical address cast to a uchar * for all architectures except AVR32,
+    which converts the physical address to an uncached virtual mapping.
+    unmap_physmem() is a no-op on all architectures, but if any
+    architecture needs to do such mappings through the TLB, this is the
+    hook where those TLB entries can be invalidated.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit cdbaefb5f5f03e54455d0439dcf6dbd97ead1f9d
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Dec 13 12:56:32 2007 +0100
+
+    cfi_flash: Introduce read and write accessors
+
+    Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use
+    them to access the flash memory. This makes it clearer when the flash
+    is actually being accessed; merely dereferencing a volatile pointer
+    looks just like any other kind of access.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 812711ce6b3a386125dcf0d6a59588e461abbb87
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Dec 13 12:56:31 2007 +0100
+
+    Implement __raw_{read,write}[bwl] on all architectures
+
+    This adds implementations of __raw_read[bwl] and __raw_write[bwl] to
+    m68k, ppc, nios and nios2. The m68k and ppc implementations were taken
+    from Linux.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit be60a9021c82fc5aecd5b2b1fc96f70a9c81bbcd
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Sat Oct 6 18:55:36 2007 +0200
+
+    cfi_flash: Reorder functions and eliminate extra prototypes
+
+    Reorder the functions in cfi_flash.c so that each function only uses
+    functions that have been defined before it. This allows the static
+    prototype declarations near the top to be eliminated and might allow
+    gcc to do a better job inlining functions.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 3055793bcbdf24b1f8117f606ffb766d32eb766f
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Dec 13 12:56:29 2007 +0100
+
+    cfi_flash: Make some needlessly global functions static
+
+    Make functions not declared in any header file static.
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 7e5b9b471518c5652febc68ba62b432193d6abf4
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date:	Thu Dec 13 12:56:28 2007 +0100
+
+    cfi_flash: Break long lines
+
+    This patch tries to keep all lines in the cfi_flash driver below 80
+    columns. There are a few lines left which don't fit this requirement
+    because I couldn't find any trivial way to break them (i.e. it would
+    take some restructuring, which I intend to do in a later patch.)
+
+    Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 42026c9cb3a76849b41e6e24abfb7b56807a5c1a
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Dec 11 13:59:57 2007 +0100
+
+    CFI: synchronize command offsets with Linux CFI driver
+
+    Fixes non-working CFI Flash on the Inka4x0 board.
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Dec 7 12:17:34 2007 -0600
+
+    Handle MPC85xx PCIe reset errata (PCI-Ex 38)
+
+    On the MPC85xx boards that have PCIe enable the PCIe errata fix.
+    (MPC8544DS, MPC8548CDS, MPC8568MDS).
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Dec 7 12:04:30 2007 -0600
+
+    Update Freescale MPC85xx ADS/CDS/MDS board config
+
+    * Enabled CONFIG_CMD_ELF
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d435793229ce29a42797c1edc39f5b34f987f91a
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Dec 7 04:59:26 2007 -0600
+
+    Handle Asynchronous DDR clock on 85xx
+
+    The MPC8572 introduces the concept of an asynchronous DDR clock with
+    regards to the platform clock.
+
+    Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
+    mode.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 10:34:28 2007 -0600
+
+    Update Freescale MPC85xx ADS/CDS/MDS board config
+
+    * Removed some misc environment setup
+    * Enabled CONFIG_CMDLINE_EDITING
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 415a613babb84d5e5d5b42e8e553868c71fc3a64
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 10:47:44 2007 -0600
+
+    Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale.
+
+    Minor path corrections needed to ensure buildability.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c2d943ffbfd3359b3b45d177b437379d2cb86fbf
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 10:16:18 2007 -0600
+
+    Move the MPC8540 ADS board under board/freescale.
+
+    Minor path corrections needed to ensure buildability.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 870ceac5b3a3486c109396e005af81ae762b5710
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 10:14:50 2007 -0600
+
+    Move the MPC8560 ADS board under board/freescale.
+
+    Minor path corrections needed to ensure buildability.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit acbca876fb3fec25cd9c55b0efc81ff618ff5262
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 10:13:47 2007 -0600
+
+    Move the MPC8568 MDS board under board/freescale.
+
+    Minor path corrections needed to ensure buildability.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a853d56c59b33415304531443633808736acfc6e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 02:18:59 2007 -0600
+
+    Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx
+
+    We already had defines for LAWAR_TRGT_IF_* that we should use
+    rather than creating new ones.  Also, added some missing defines for
+    PCIE targets.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 04db400892da37b76a585e332a0c137954ad2015
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 02:10:09 2007 -0600
+
+    Stop using immap_t on 85xx
+
+    In the future the offsets to various blocks may not be in same location.
+    Move to using CFG_MPC85xx_*_ADDR as the base of the registers
+    instead of getting it via &immap.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2714223f8e04ab3e4133ff65872eef366d90bfea
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 01:23:09 2007 -0600
+
+    Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c480861bf000156e6a3e932c258db59ff2212dd3
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 01:06:19 2007 -0600
+
+    Update MPC8568 MDS to use libfdt
+
+    Updated the MPC8568 MDS config to use libfdt and assume use of aliases for
+    ethernet, pci, and serial for the various fixups that are done.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1563f56e0c68f6920f956382d6d13bee3f01c0f7
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed Nov 14 15:52:06 2007 -0500
+
+    Add PCI Express support on MPC8568MDS
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b90d25497625b90ffa3f2911a0895ca237556ff5
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 00:11:44 2007 -0600
+
+    Update MPC85xx CDS to use libfdt
+
+    Updated the MPC85xx CDS config to use libfdt and assume use of aliases for
+    ethernet, pci, and serial for the various fixups that are done.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0fd5ec66b10521a057ad73e69ab5f0f9eafba255
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Nov 28 22:54:27 2007 -0600
+
+    Update MPC8540 ADS to use libfdt
+
+    Updated the MPC8540 ADS config to use libfdt and assume use of aliases for
+    ethernet, pci, and serial for the various fixups that are done.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5ce715802f6c50dc78b3405b92f184b1e3710519
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Nov 28 22:40:31 2007 -0600
+
+    Update MPC8560 ADS to use libfdt
+
+    Updated the MPC8560 ADS config to use libfdt and assume use of aliases for
+    ethernet, pci, and serial for the various fixups that are done.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit aafeefbdb8b029f5ca2a195598d0a501a606eea9
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Nov 28 00:36:33 2007 -0600
+
+    Stop using immap_t for cpm offset on 85xx
+
+    In the future the offsets to various blocks may not be in same location.
+    Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
+    instead of getting it via &immap->im_cpm.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f59b55a5b8fcadaa99781ba48e7a38e956afa527
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Nov 27 23:25:02 2007 -0600
+
+    Stop using immap_t for guts offset on 85xx
+
+    In the future the offsets to various blocks may not be in same location.
+    Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
+    instead of getting it via &immap->im_gur.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 50c03c8cf494d91cdec39670d95337c743e16ec9
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Nov 27 22:42:34 2007 -0600
+
+    Update MPC8544 DS config
+
+    * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
+    * Removed some misc environment setup
+    * Moved to using fdtfile & fdtaddr as fdt env var names
+    * Enabled CONFIG_CMDLINE_EDITING
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit addce57e2e4c49e77ffb2020a84690713bb18b47
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 26 17:12:24 2007 -0600
+
+    Update MPC8544DS to use libfdt
+
+    Updated the MPC8544DS config to use libfdt and assume use of aliases for
+    ethernet, pci, and serial for the various fixups that are done.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f852ce72f100cabd1f11c21c085a0ad8eca9fb65
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Nov 29 00:15:30 2007 -0600
+
+    Add libfdt based ft_cpu_setup for mpc85xx
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Dec 8 08:25:09 2007 +0100
+
+    CFI: Coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22
+Author: Michael Schwingen <michael@schwingen.org>
+Date:	Fri Dec 7 23:35:02 2007 +0100
+
+    CFI: support JEDEC flash roms in CFI-flash framework
+
+    The following patch adds support for non-CFI flash ROMS, by hooking into the
+    CFI flash code and using most of its code, as recently discussed here in the
+    thread "Mixing CFI and non-CFI flashs".
+
+    Signed-off-by: Michael Schwingen <michael@schwingen.org>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c01b17dd856fa120b2970f50d9598546a4927ec3
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Wed Nov 28 21:24:50 2007 -0500
+
+    Conditionally compile fdt_fixup_ethernet()
+
+    Fix compiler warnings: On boards that don't have ethernets defined,
+    don't compile fdt_fixup_ethernet().
+
+commit 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Nov 27 21:59:46 2007 -0600
+
+    Convert boards that set memory node to use fdt_fixup_memory()
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 151c8b09b35eebe8fd9139cb6c1d91c27b22f058
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 26 17:06:15 2007 -0600
+
+    Added fdt_fixup_stdout that uses aliases to set linux,stdout-path
+
+    We use a combination of the serialN alias and CONFIG_CONS_INDEX to
+    determine which serial alias we should set linux,stdout-path to.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 3c9272813fad84c691d0e4989bb18a3ffebdebfc
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 26 14:57:45 2007 -0600
+
+    Add common memory fixup function
+
+    Add the function fdt_fixup_memory() to fixup the /memory node of the fdt
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9c9109e7fcf7ac2ca19c95b8ac54b8d1c773b157
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 26 11:19:12 2007 -0600
+
+    Conditionally compile fdt_support.c
+
+    Modify common/Makefile to conditionally compile fdt_support.c based
+    on CONFIG_OF_LIBFDT.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d88e7ba0980773479e1a64badb293116071b7ef0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 26 10:41:40 2007 -0600
+
+    Fix build breakage due to libfdt import
+
+    The IDS8247 got lost in the update and need an API update
+    do to rename of functions in libfdt.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 28f384b171bbf1fb2dafb1046e6d259a6b2f8714
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Fri Nov 23 19:43:20 2007 -0500
+
+    Add spaces around the = in the fdt print format.
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 29592ecba3b932b9b152bcec6c0c0806412db4a3
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Dec 7 01:25:38 2007 +0900
+
+    sh: Moved driver of the SuperH dependence
+
+    The composition of the directory in the drivers/ changed.
+    I moved SuperH serial driver and marubun PCMCIA driver.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 41be969f4957115ed7b1fe8b890bfaee99d7a7a2
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Dec 6 10:21:19 2007 +0100
+
+    Release v1.3.1
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cf5933ba1e97a1cd8f5f24070e820f21d976eaeb
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Dec 6 10:21:03 2007 +0100
+
+    ADS5121 Board: fix compile problem.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Dec 3 00:15:28 2007 +0100
+
+    Prepare for 1.3.1-rc1
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 260eea5676ca46903a335686cc020b29c4ca46fe
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Thu Nov 29 01:21:54 2007 +0900
+
+    sh: Add SuperH boards maintainer to MAINTAINERS file
+
+    Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit aa9c4f1d22701a92347c1c81f34d12c8ad3a3747
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Thu Nov 29 00:13:04 2007 +0900
+
+    sh: Add ms7750se support in MAKEALL
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c7144373427a178332bf9754131c8c34c52c200a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Nov 27 09:44:53 2007 +0100
+
+    sh: Add sh3 and sh4 support in MAKEALL
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 130080874a3d28450098481a262c5f7c855e908d
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Nov 25 02:51:17 2007 +0900
+
+    sh: Add document for SuperH.
+
+    This document is a summary of information concerning SuperH of U-Boot.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Nov 25 02:39:31 2007 +0900
+
+    sh: Add marubun's pcmcia driver
+
+    Marubun pcmcia is a chip for PCMCIA used with SuperH.
+    Of course, this can be used even by other architectures.
+    When use this driver, came to be able to use CompactFlash
+    and Ethernet.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit febd86b969b975289ed948f1ac0eb9722da41ced
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Nov 25 02:32:13 2007 +0900
+
+    sh: Update SuperH SCIF driver
+
+    - Changed volatile unsigned to vu_.
+    - Changed Makefile for kconfig.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
 commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Mon Nov 26 19:18:21 2007 +0100
@@ -1927,6 +2611,56 @@ Date:	Mon Sep 24 00:08:37 2007 +0200
 
     synchronizition with mainline
 
+commit eda3e1e6619ad0bee94ae4b16c99d88e77e2af13
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Sep 23 02:42:38 2007 +0900
+
+    sh: Add support command of ide with sh
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit d91ea45d15cf8e0987456bd211ffbb650824b6f1
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Sep 23 02:38:42 2007 +0900
+
+    sh: Update Makefile
+
+    Add support MS7722SE01 to Makefile.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Sep 23 02:31:13 2007 +0900
+
+    sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 047375bfa4c3052fa50a748da7ff89e9dad3b364
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Sep 23 02:19:24 2007 +0900
+
+    sh: Update MS7750SE01 platform
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 516ad760db3553766267ada01b7d5d727faa4bbd
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Sep 23 02:17:08 2007 +0900
+
+    sh: Remove comment out code from include/asm-sh/cpu_sh4.h
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit b02bad128669e567fce87d8df823b06a0144b8db
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Sep 23 02:12:30 2007 +0900
+
+    sh: Update core code of SuperH.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
 commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu Sep 20 00:04:14 2007 +0200
@@ -8634,6 +9368,24 @@ Date:	Tue May 15 07:55:42 2007 -0700
 
      Fix to compile JSE against 20070514 git of u-boot
 
+commit 69df3c4da0c93017cceb25a366e794570bd0ed98
+Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)>
+Date:	Sun May 13 21:01:03 2007 +0900
+
+    sh: MS7750SE support.
+
+    This adds support for the Hitachi MS7750SE.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0b135cfc2e524dc249b75057b55dd4cc09842e27
+Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)>
+Date:	Sun May 13 20:58:00 2007 +0900
+
+    sh: First support code of SuperH.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
 commit 61936667e86a250ae12fd2dc189d3588f0a59e0b
 Author: Stefan Roese <sr@denx.de>
 Date:	Fri May 11 12:01:49 2007 +0200

CREDITS

@@ -117,7 +117,7 @@ N: Arun Dharankar
 E: ADharankar@ATTBI.Com
 D: threads / scheduler example code
 
-N: Kári Davíðsson
+N: K?ri Dav??sson
 E: kd@flaga.is
 D: FLAGA DM Support
 
@@ -143,7 +143,7 @@ E: info@elste.org
 D: Port for the ModNET50 Board, NET+50 CPU Port
 W: http://www.imms.de
 
-N: Daniel Engström
+N: Daniel Engstr?m
 E: daniel@omicron.se
 D: x86 port, Support for sc520_cdp board
 
@@ -334,7 +334,7 @@ N: Frank Morauf
 E: frank.morauf@salzbrenner.com
 D: Support for Embedded Planet RPX Super Board
 
-N: David Müller
+N: David M?ller
 E: d.mueller@elsoft.ch
 D: Support for Samsung ARM920T SMDK2410 eval board
 
@@ -499,3 +499,8 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
+
+N: Nobuhiro Iwamatsu
+E: iwamatsu@nigauri.org
+D: Support for SuperH, MS7750SE01 and  MS7722SE01 boards.
+W: http://www.nigauri.org/~iwamatsu/

MAINTAINERS

@@ -636,7 +636,22 @@ Hayden Fraser <Hayden.Fraser@freescale.com>
 
 Haavard Skinnemoen <hskinnemoen@atmel.com>
 
-	ATSTK1000		AT32AP7000
+	ATSTK1000		AT32AP7xxx
+	ATSTK1002		AT32AP7000
+	ATSTK1003		AT32AP7001
+	ATSTK1004		AT32AP7002
+
+#########################################################################
+# SuperH Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
+
+	MS7750SE		SH7750
+	MS7722SE		SH7722
 
 #########################################################################
 # End of MAINTAINERS list						#

MAKEALL

@@ -647,6 +647,8 @@ LIST_coldfire="			\
 
 LIST_avr32="		\
 	atstk1002	\
+	atstk1003	\
+	atstk1004	\
 "
 
 #########################################################################
@@ -660,6 +662,23 @@ LIST_blackfin="		\
 	bf561-ezkit	\
 "
 
+#########################################################################
+## SH Systems
+#########################################################################
+
+LIST_sh4="		\
+	ms7750se	\
+	ms7722se	\
+"
+
+LIST_sh3=""
+
+
+LIST_sh="		\
+	${LIST_sh3}	\
+	${LIST_sh4}	\
+"
+
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -694,7 +713,9 @@ do
 	mips|mips_el| \
 	nios|nios2| \
 	ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
-	x86|I486|TSEC)
+	x86|I486|TSEC| \
+	sh|sh4|sh3 \
+	)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -152,6 +152,9 @@ endif
 ifeq ($(ARCH),avr32)
 CROSS_COMPILE = avr32-linux-
 endif
+ifeq ($(ARCH),sh)
+CROSS_COMPILE = sh4-linux-
+endif
 endif
 endif
 
@@ -1928,7 +1931,7 @@ TQM834x_config:	unconfig
 #########################################################################
 
 MPC8540ADS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
 
 MPC8540EVAL_config \
 MPC8540EVAL_33_config \
@@ -1952,7 +1955,7 @@ MPC8540EVAL_66_slave_config:      unconfig
 	@$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
 
 MPC8560ADS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale
 
 MPC8541CDS_legacy_config \
 MPC8541CDS_config:	unconfig
@@ -1962,7 +1965,7 @@ MPC8541CDS_config:	unconfig
 		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
 		echo "... legacy" ; \
 	fi
-	@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
+	@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale
 
 MPC8544DS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
@@ -1975,7 +1978,7 @@ MPC8548CDS_config:	unconfig
 		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
 		echo "... legacy" ; \
 	fi
-	@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
+	@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale
 
 MPC8555CDS_legacy_config \
 MPC8555CDS_config:	unconfig
@@ -1985,10 +1988,10 @@ MPC8555CDS_config:	unconfig
 		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
 		echo "... legacy" ; \
 	fi
-	@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
+	@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale
 
 MPC8568MDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
 
 PM854_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
@@ -2673,7 +2676,30 @@ bf561-ezkit_config:	unconfig
 #########################################################################
 
 atstk1002_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
+atstk1003_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
+atstk1004_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
+#########################################################################
+#########################################################################
+#########################################################################
+
+#########################################################################
+## sh4 (Renesas SuperH)
+#########################################################################
+ms7750se_config: unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MS7750SE 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 ms7750se
+
+ms7722se_config :       unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MS7722SE 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 ms7722se
 
 #########################################################################
 #########################################################################

README

@@ -235,9 +235,7 @@ The following options need to be configured:
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
-		Define exactly one of
-		CONFIG_ATSTK1002
-
+		Define exactly one, e.g. CONFIG_ATSTK1002
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
 		Define exactly one of

board/cm5200/cm5200.c

@@ -263,7 +263,6 @@ static void ft_blob_update(void *blob, bd_t *bd)
 {
 	int len, ret, nodeoffset = 0;
 	char module_name[MODULE_NAME_MAXLEN] = {0};
-	ulong memory_data[2] = {0};
 
 	compose_module_name(hw_id, module_name);
 	len = strlen(module_name) + 1;
@@ -273,22 +272,12 @@ static void ft_blob_update(void *blob, bd_t *bd)
 	printf("ft_blob_update(): cannot set /model property err:%s\n",
 		fdt_strerror(ret));
 
-	memory_data[0] = cpu_to_be32(bd->bi_memstart);
-	memory_data[1] = cpu_to_be32(bd->bi_memsize);
+	ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
-	nodeoffset = fdt_path_offset (blob, "/memory");
-	if (nodeoffset >= 0) {
-		ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
-					sizeof(memory_data));
-	if (ret < 0)
+	if (ret < 0) {
 		printf("ft_blob_update): cannot set /memory/reg "
 			"property err:%s\n", fdt_strerror(ret));
 	}
-	else {
-		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /memory node "
-		"err:%s\n", fdt_strerror(nodeoffset));
-	}
 }
 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
 

board/cds/common/ft_board.c → board/freescale/common/ft_board.c

@@ -21,24 +21,29 @@
  */
 
 #include <common.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 #include "cadmus.h"
 
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
+#if defined(CONFIG_OF_BOARD_SETUP)
 static void cds_pci_fixup(void *blob)
 {
-	int len;
-	u32 *map;
-	int slot;
-	int i;
+	int node, tmp[2];
+	const char *path;
+	int len, slot, i;
+	u32 *map = NULL;
 
-	map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
-
-	if (!map)
-		map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			node = fdt_path_offset(blob, path);
+			if (node >= 0) {
+				map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+			}
+		}
+	}
 
 	if (map) {
 		len /= sizeof(u32);
@@ -50,33 +55,18 @@ static void cds_pci_fixup(void *blob)
 			 * changes depending on the slot the carrier card is in.
 			 */
 			map[3] = ((map[3] + slot - 2) % 4) + 1;
-
 			map+=7;
 		}
-	} else {
-		printf("*** Warning - No PCI node found\n");
 	}
 }
-#endif
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
-
+	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-
 	cds_pci_fixup(blob);
+#endif
 }
 #endif

board/mpc8540ads/mpc8540ads.c → board/freescale/mpc8540ads/mpc8540ads.c

@@ -30,11 +30,8 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <spd.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -77,13 +74,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    uint temp_ddrdll = 0;
 
 	    /*
@@ -125,9 +121,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -186,8 +181,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
@@ -282,8 +276,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
@@ -331,22 +324,25 @@ pci_init_board(void)
 }
 
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
 	ft_cpu_setup(blob, bd);
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
 	}
 }
 #endif

board/mpc8540ads/u-boot.lds → board/freescale/mpc8540ads/u-boot.lds

@@ -35,7 +35,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/mpc8540ads/init.o (.bootpg)
+    board/freescale/mpc8540ads/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/mpc8540ads/init.o (.text)
+    board/freescale/mpc8540ads/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)

board/cds/mpc8541cds/mpc8541cds.c → board/freescale/mpc8541cds/mpc8541cds.c

@@ -28,6 +28,8 @@
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -203,8 +205,7 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -250,7 +251,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -263,7 +263,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -293,9 +293,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -344,8 +343,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
@@ -506,3 +504,31 @@ pci_init_board(void)
 	pci_mpc85xx_init(hose);
 #endif
 }
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif

board/cds/mpc8555cds/u-boot.lds → board/freescale/mpc8541cds/u-boot.lds

@@ -34,7 +34,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/cds/mpc8555cds/init.o (.bootpg)
+    board/freescale/mpc8541cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/cds/mpc8555cds/init.o (.text)
+    board/freescale/mpc8541cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)

board/freescale/mpc8544ds/init.S

@@ -27,13 +27,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCIE1	0x00200000
-#define LAWAR_TRGT_PCIE2	0x00100000
-#define LAWAR_TRGT_PCIE3	0x00300000
-#define LAWAR_TRGT_LBC		0x00400000
-#define LAWAR_TRGT_DDR		0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -212,31 +205,31 @@ law_entry:
 	.long (4f-3f)/8
 3:
 	.long	0
-	.long	(LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+	.long	(LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
 	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	.long	(CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCIE2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	/* contains both PCIE3 MEM & IO space */
 	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
 	entry_end

board/freescale/mpc8544ds/mpc8544ds.c

@@ -29,14 +29,11 @@
 #include <asm/io.h>
 #include <spd.h>
 #include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/pixis.h"
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -52,10 +49,9 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %x\n",&gur->porpllsr);
@@ -149,8 +145,7 @@ int first_free_busno=0;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy)
 	return val;
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
+
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
 	ft_cpu_setup(blob, bd);
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
 #ifdef CONFIG_PCI1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
-#endif
-#ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
-		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCIE2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
-		debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_PCIE1
+		path = fdt_getprop(blob, node, "pci2", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCIE3
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
-		debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci3", NULL);
+		if (path) {
+			tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
+	}
 }
 #endif

board/cds/mpc8548cds/init.S → board/freescale/mpc8548cds/init.S

@@ -28,13 +28,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCI2		0x00100000
-#define LAWAR_TRGT_PCIE		0x00200000
-#define LAWAR_TRGT_RIO		0x00c00000
-#define LAWAR_TRGT_LBC		0x00400000
-#define LAWAR_TRGT_DDR		0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -232,39 +225,39 @@ law_entry:
 	.long (4f-3f)/8
 3:
 	.long  0
-	.long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+	.long  (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
 #ifdef CFG_PCI1_MEM_PHYS
 	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 #ifdef CFG_PCI2_MEM_PHYS
 	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 #ifdef CFG_PCIE1_MEM_PHYS
 	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 #ifdef CFG_RIO_MEM_PHYS
 	.long	(CFG_RIO_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
 #endif
 4:
 	entry_end

board/cds/mpc8548cds/mpc8548cds.c → board/freescale/mpc8548cds/mpc8548cds.c

@@ -29,14 +29,13 @@
 #include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -55,9 +54,8 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -96,7 +94,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -109,7 +106,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -139,9 +136,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -177,8 +173,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
@@ -330,8 +325,7 @@ int first_free_busno=0;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 
@@ -524,30 +518,30 @@ int last_stage_init(void)
 }
 
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_pci_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
-
+	int node, tmp[2];
+	const char *path;
 
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
 #ifdef CONFIG_PCI1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
-
 #ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
-		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
+	}
 }
 #endif

board/cds/mpc8548cds/u-boot.lds → board/freescale/mpc8548cds/u-boot.lds

@@ -34,7 +34,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/cds/mpc8548cds/init.o (.bootpg)
+    board/freescale/mpc8548cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/cds/mpc8548cds/init.o (.text)
+    board/freescale/mpc8548cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)

board/cds/mpc8555cds/mpc8555cds.c → board/freescale/mpc8555cds/mpc8555cds.c

@@ -26,6 +26,8 @@
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -201,8 +203,7 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -248,7 +249,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -261,7 +261,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -291,9 +291,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -342,8 +341,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
@@ -506,3 +504,31 @@ pci_init_board(void)
 	pci_mpc85xx_init(hose);
 #endif
 }
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif

board/cds/mpc8541cds/u-boot.lds → board/freescale/mpc8555cds/u-boot.lds

@@ -34,7 +34,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/cds/mpc8541cds/init.o (.bootpg)
+    board/freescale/mpc8555cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/cds/mpc8541cds/init.o (.text)
+    board/freescale/mpc8555cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)

board/mpc8560ads/mpc8560ads.c → board/freescale/mpc8560ads/mpc8560ads.c

@@ -32,10 +32,8 @@
 #include <ioports.h>
 #include <spd.h>
 #include <miiphy.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -278,13 +276,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    uint temp_ddrdll = 0;
 
 	    /*
@@ -326,9 +323,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -387,8 +383,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
@@ -483,8 +478,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
@@ -548,35 +542,25 @@ pci_init_board(void)
 }
 
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_soc_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
-
-	if (p != NULL)
-		*p = cpu_to_be32(bd->bi_brgfreq);
-
-	p = ft_get_prop(blob,
-			"/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
-			&len);
-	if (p != NULL)
-		*p = cpu_to_be32(bd->bi_baudrate);
-
-	p = ft_get_prop(blob,
-			"/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
-			&len);
-	if (p != NULL)
-		*p = cpu_to_be32(bd->bi_baudrate);
-}
-
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
+	int node, tmp[2];
+	const char *path;
+
 	ft_cpu_setup(blob, bd);
-	ft_soc_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
 }
 #endif

board/mpc8560ads/u-boot.lds → board/freescale/mpc8560ads/u-boot.lds

@@ -35,7 +35,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/mpc8560ads/init.o (.bootpg)
+    board/freescale/mpc8560ads/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/mpc8560ads/init.o (.text)
+    board/freescale/mpc8560ads/init.o (.text)
     cpu/mpc85xx/commproc.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)

board/mpc8568mds/Makefile → board/freescale/mpc8568mds/Makefile

@@ -29,9 +29,7 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o \
-	bcsr.o \
-	ft_board.o
+COBJS	:= $(BOARD).o bcsr.o
 
 SOBJS	:= init.o
 

board/mpc8568mds/init.S → board/freescale/mpc8568mds/init.S

@@ -28,7 +28,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -216,15 +215,14 @@ tlb1_entry:
 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
 #define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
-#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
 #define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
-#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
+#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
 #define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))

board/mpc8568mds/mpc8568mds.c → board/freescale/mpc8568mds/mpc8568mds.c

@@ -26,9 +26,12 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <i2c.h>
 #include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "bcsr.h"
 
@@ -133,7 +136,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -146,7 +148,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -176,9 +178,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -211,8 +212,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 
@@ -337,16 +337,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
 };
 #endif
 
-static struct pci_controller hose[] = {
-	{
+static struct pci_controller pci1_hose = {
 #ifndef CONFIG_PCI_PNP
 	config_table: pci_mpc8568mds_config_table,
 #endif
-	}
 };
-
 #endif	/* CONFIG_PCI */
 
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif  /* CONFIG_PCIE1 */
+
+int first_free_busno = 0;
+
 /*
  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
  */
@@ -389,11 +392,164 @@ pib_init(void)
 	asm("eieio");
 }
 
+#ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
-#ifdef CONFIG_PCI
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCI1
+{
 	pib_init();
-	pci_mpc85xx_init(hose);
+
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci1_hose;
+
+	uint pci_32 = 1;      /* PORDEVSR[15] */
+	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
+	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
+
+	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+	uint pci_speed = 66666000;
+
+	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter"
+			);
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+				CFG_PCI_MEMORY_BUS,
+				CFG_PCI_MEMORY_PHYS,
+				CFG_PCI_MEMORY_SIZE,
+				PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+				CFG_PCI1_MEM_BASE,
+				CFG_PCI1_MEM_PHYS,
+				CFG_PCI1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+				CFG_PCI1_IO_BASE,
+				CFG_PCI1_IO_PHYS,
+				CFG_PCI1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		first_free_busno = hose->last_busno+1;
+		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+	} else {
+	printf ("    PCI: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 #endif
+
+#ifdef CONFIG_PCIE1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pcie1_hose;
+	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+	int pcie_configured  = io_sel >= 1;
+
+	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n    PCIE connected to slot as %s (base address %x)",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
+		}
+		printf ("\n");
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+				CFG_PCI_MEMORY_BUS,
+				CFG_PCI_MEMORY_PHYS,
+				CFG_PCI_MEMORY_SIZE,
+				PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+				CFG_PCIE1_MEM_BASE,
+				CFG_PCIE1_MEM_PHYS,
+				CFG_PCIE1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+				CFG_PCIE1_IO_BASE,
+				CFG_PCIE1_IO_PHYS,
+				CFG_PCIE1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+
+		first_free_busno=hose->last_busno+1;
+
+	} else {
+		printf ("    PCIE: disabled\n");
+	}
 }
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	ft_cpu_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_PCIE1
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif

board/mpc8568mds/u-boot.lds → board/freescale/mpc8568mds/u-boot.lds

@@ -37,7 +37,7 @@ SECTIONS
   .bootpg 0xFFFFF000:
   {
 	cpu/mpc85xx/start.o	(.bootpg)
-	board/mpc8568mds/init.o (.bootpg)
+	board/freescale/mpc8568mds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -67,7 +67,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/mpc8568mds/init.o (.text)
+    board/freescale/mpc8568mds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)

board/ids8247/ids8247.c

@@ -329,25 +329,14 @@ nand_init (void)
  */
 void ft_blob_update(void *blob, bd_t *bd)
 {
-	int ret, nodeoffset = 0;
-	ulong memory_data[2] = {0};
+	int ret;
 
-	memory_data[0] = cpu_to_be32(bd->bi_memstart);
-	memory_data[1] = cpu_to_be32(bd->bi_memsize);
+	ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
-	nodeoffset = fdt_find_node_by_path (blob, "/memory");
-	if (nodeoffset >= 0) {
-		ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
-					sizeof(memory_data));
-	if (ret < 0)
+	if (ret < 0) {
 		printf("ft_blob_update): cannot set /memory/reg "
 			"property err:%s\n", fdt_strerror(ret));
 	}
-	else {
-		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /memory node "
-		"err:%s\n", fdt_strerror(nodeoffset));
-	}
 }
 
 void ft_board_setup(void *blob, bd_t *bd)

board/mpc8540eval/mpc8540eval.c

@@ -35,8 +35,7 @@ long int fixed_sdram (void);
 int board_pre_init (void)
 {
 #if defined(CONFIG_PCI)
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile ccsr_pcix_t *pci = &immr->im_pcix;
+	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
 	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -68,14 +67,13 @@ long int initdram (int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur= &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 #endif
 
 #if defined(CONFIG_DDR_DLL)
@@ -138,8 +136,7 @@ long int initdram (int board_type)
 		 * enable errors */
 		uint *p = 0;
 		uint i = 0;
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 		dma_init();
 		for (*p = 0; p < (uint *)(8 * 1024); p++) {
 			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -222,8 +219,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
 #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;

board/ms7722se/Makefile

@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7722se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/ms7722se/config.mk

@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000

board/ms7722se/lowlevel_init.S

@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ *  Board specific low level init code, called _very_ early in the
+ *  startup sequence. Relocation to SDRAM has not happened yet, no
+ *  stack is available, bss section has not been initialised, etc.
+ *
+ *  (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	mov.l	CCR_A, r1	! Address of Cache Control Register
+	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	mov.l	r0, @r1
+
+	mov.l	MMUCR_A, r1	! Address of MMU Control Register
+	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
+	mov.l	MSTPCR0_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
+	mov.l	MSTPCR2_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	SBSCR_A, r1	!
+	mov.w	SBSCR_D, r0	!
+	mov.w	r0, @r1
+
+	mov.l	PSCR_A, r1	!
+	mov.w	PSCR_D, r0	!
+	mov.w	r0, @r1
+
+!	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+!	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+!	mov.w	r0, @r1
+
+	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
+	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	mov.w	r0, @r1
+
+	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	mov.l	FRQCR_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	CCR_A, r1		! Address of Cache Control Register
+	mov.l	CCR_D_2, r0	! ??
+	mov.l	r0, @r1
+
+bsc_init:
+
+	mov.l	PSELA_A, r1
+	mov.w	PSELA_D, r0
+	mov.w	r0, @r1
+
+	mov.l	DRVCR_A, r1
+	mov.w	DRVCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PCCR_A, r1
+	mov.w	PCCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PECR_A, r1
+	mov.w	PECR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PJCR_A, r1
+	mov.w	PJCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PXCR_A, r1
+	mov.w	PXCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	CMNCR_A, r1	! CMNCR address -> R1
+	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	r0, @r1		! CMNCR set
+
+	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
+	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	r0, @r1		! CS0BCR set
+
+	mov.l	CS2BCR_A, r1	! CS2BCR address -> R1
+	mov.l	CS2BCR_D, r0	! CS2BCR data    -> R0
+	mov.l	r0, @r1		! CS2BCR set
+
+	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
+	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
+	mov.l	r0, @r1		! CS4BCR set
+
+	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
+	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	r0, @r1		! CS5ABCR set
+
+	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
+	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	r0, @r1		! CS5BBCR set
+
+	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
+	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	r0, @r1		! CS6ABCR set
+
+	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
+	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	r0, @r1		! CS0WCR set
+
+	mov.l	CS2WCR_A, r1	! CS2WCR address -> R1
+	mov.l 	CS2WCR_D, r0	! CS2WCR data    -> R0
+	mov.l	r0, @r1		! CS2WCR set
+
+	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
+	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	r0, @r1		! CS4WCR set
+
+	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
+	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	r0, @r1		! CS5AWCR set
+
+	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
+	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	r0, @r1		! CS5BWCR set
+
+	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
+	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	r0, @r1		! CS6AWCR set
+
+	! SDRAM initialization
+	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
+	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
+	mov.l	r0, @r1		! SB_SDCR set
+
+	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
+	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
+	mov.l	r0, @r1		! SB_SDWCR set
+
+	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
+	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
+	mov.l	r0, @r1		! SB_SDPCR set
+
+	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
+	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
+	mov.l	r0, @r1		! SB_RTCOR set
+
+	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
+	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
+	mov.l	r0, @r1		! SB_RTCSR set
+
+	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
+	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov.b	r0, @r1		! SDMR3 set
+
+	! BL bit off (init = ON)  (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	mov	#0, r0
+
+	.align	2
+
+CCR_A:		.long	CCR
+MMUCR_A:	.long	MMUCR
+MSTPCR0_A:	.long	MSTPCR0
+MSTPCR2_A:	.long	MSTPCR2
+SBSCR_A:	.long	SBSCR
+PSCR_A:		.long	PSCR
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+
+CCR_D:		.long	0x00000800
+CCR_D_2:	.long	0x00000103
+MMUCR_D:	.long	0x00000004
+MSTPCR0_D:	.long	0x00001001
+MSTPCR2_D:	.long	0xffffffff
+FRQCR_D:	.long	0x07022538
+
+PSELA_A:	.long   0xa405014E
+PSELA_D:	.word   0x0A10
+	.align 2
+
+DRVCR_A:	.long   0xa405018A
+DRVCR_D:	.word   0x0554
+	.align 2
+
+PCCR_A:		.long   0xa4050104
+PCCR_D:		.word   0x8800
+	.align 2
+
+PECR_A:		.long   0xa4050108
+PECR_D:		.word   0x0000
+	.align 2
+
+PJCR_A:		.long   0xa4050110
+PJCR_D:		.word   0x1000
+	.align 2
+
+PXCR_A:		.long   0xa4050148
+PXCR_D:		.word   0x0AAA
+	.align 2
+
+CMNCR_A:	.long	CMNCR
+CMNCR_D:	.long	0x00000013
+CS0BCR_A:	.long	CS0BCR		! Flash bank 1
+CS0BCR_D:	.long	0x24920400
+CS2BCR_A:	.long	CS2BCR		! SRAM
+CS2BCR_D:	.long	0x24920400
+CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
+CS4BCR_D:	.long	0x24920400
+CS5ABCR_A:	.long	CS5ABCR		! Ext slot
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_A:	.long	CS5BBCR		! USB controller
+CS5BBCR_D:	.long	0x24920400
+CS6ABCR_A:	.long	CS6ABCR		! Ethernet
+CS6ABCR_D:	.long	0x24920400
+
+CS0WCR_A:	.long	CS0WCR
+CS0WCR_D:	.long	0x00000300
+CS2WCR_A:	.long	CS2WCR
+CS2WCR_D:	.long	0x00000300
+CS4WCR_A:	.long	CS4WCR
+CS4WCR_D:	.long	0x00000300
+CS5AWCR_A:	.long	CS5AWCR
+CS5AWCR_D:	.long	0x00000300
+CS5BWCR_A:	.long	CS5BWCR
+CS5BWCR_D:	.long	0x00000300
+CS6AWCR_A:	.long	CS6AWCR
+CS6AWCR_D:	.long	0x00000300
+
+SDCR_A:		.long	SBSC_SDCR
+SDCR_D:		.long	0x00020809
+SDWCR_A:	.long	SBSC_SDWCR
+SDWCR_D:	.long	0x00164d0d
+SDPCR_A:	.long	SBSC_SDPCR
+SDPCR_D:	.long	0x00000087
+RTCOR_A:	.long	SBSC_RTCOR
+RTCOR_D:	.long	0xA55A0034
+RTCSR_A:	.long	SBSC_RTCSR
+RTCSR_D:	.long	0xA55A0010
+SDMR3_A:	.long	0xFE500180
+
+	.align	1
+
+SBSCR_D:	.word	0x0040
+PSCR_D:		.word	0x0000
+RWTCSR_D_1:	.word	0xA507
+RWTCSR_D_2:	.word	0xA507
+RWTCNT_D:	.word	0x5A00
+
+SR_MASK_D:	.long	0xEFFFFF0F

board/ms7722se/ms7722se.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/ms7722se.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#define LED_BASE	0xB0800000
+
+int checkboard(void)
+{
+	puts("BOARD: Hitachi UL MS7722SE\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Setup PTXMD[1:0] for /CS6A */
+	outw(inw(PXCR) & ~0xf000, PXCR);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+	*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
+}

board/ms7722se/u-boot.lds

@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}

board/ms7750se/Makefile

@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7750se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+	$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################

board/ms7750se/config.mk

@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x8FFC0000

board/ms7750se/lowlevel_init.S

@@ -0,0 +1,179 @@
+/*
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_CPU_SH7751
+#define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MARUBUN_PCCARD
+#define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#else /* CONFIG_MARUBUN_PCCARD */
+#define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#endif /* CONFIG_MARUBUN_PCCARD */
+#define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#else /* CONFIG_CPU_SH7751 */
+#define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
+#define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#endif /* CONFIG_CPU_SH7751 */
+
+	.global lowlevel_init
+	.text
+	.align  2
+
+lowlevel_init:
+
+	mov.l   CCR_A, r1               ! CCR Address
+	mov.l   CCR_D_DISABLE, r0       ! CCR Data
+	mov.l   r0, @r1
+
+init_bsc:
+	mov.l	FRQCR_A,r1	/* FRQCR Address */
+	mov.l	FRQCR_D,r0	/* FRQCR Data */
+	mov.w	r0,@r1
+
+	mov.l	BCR1_A,r1	/* BCR1 Address */
+	mov.l	BCR1_D,r0	/* BCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	BCR2_A,r1	/* BCR2 Address */
+	mov.l	BCR2_D,r0	/* BCR2 Data */
+	mov.w	r0,@r1
+
+	mov.l	WCR1_A,r1	/* WCR1 Address */
+	mov.l	WCR1_D,r0	/* WCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR2_A,r1	/* WCR2 Address */
+	mov.l	WCR2_D,r0	/* WCR2 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR3_A,r1	/* WCR3 Address */
+	mov.l	WCR3_D,r0	/* WCR3 Data */
+	mov.l	r0,@r1
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D1,r0	/* MCR Data1 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	! Do you need PCMCIA setting?
+	! If so, please add the lines here...
+
+	mov.l	RTCNT_A,r1	/* RTCNT Address */
+	mov.l	RTCNT_D,r0	/* RTCNT Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCOR_A,r1	/* RTCOR Address */
+	mov.l	RTCOR_D,r0	/* RTCOR Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCSR_A,r1	/* RTCSR Address */
+	mov.l	RTCSR_D,r0	/* RTCSR Data */
+	mov.w	r0,@r1
+
+	mov.l	RFCR_A,r1	/* RFCR Address */
+	mov.l	RFCR_D,r0	/* RFCR Data */
+	mov.w	r0,@r1		/* Clear reflesh counter */
+	/* Wait DRAM refresh 30 times */
+	mov	#30,r3
+1:
+	mov.w	@r1,r0
+	extu.w	r0,r2
+	cmp/hi	r3,r2
+	bf	1b
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D2,r0	/* MCR Data2 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	rts
+	 nop
+
+	.align	2
+
+CCR_A:          .long   CCR
+CCR_D_DISABLE:  .long   0x0808
+FRQCR_A:	.long	FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_TYPE_R
+		.long	0x00000e1a	/* 12:3:3 */
+#else	/* CONFIG_CPU_TYPE_R */
+#ifdef CONFIG_GOOD_SESH4
+		.long	0x00000e13	/* 6:2:1 */
+#else
+		.long	0x00000e23	/* 6:1:1 */
+#endif
+#endif	/* CONFIG_CPU_TYPE_R */
+
+BCR1_A:		.long	BCR1
+BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
+BCR2_A:		.long	BCR2
+BCR2_D:		.long	BCR2_D_VALUE	/* Bus width settings */
+WCR1_A:		.long	WCR1
+WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
+WCR2_A:		.long	WCR2
+WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
+WCR3_A:		.long	WCR3
+WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
+RTCSR_A:	.long	RTCSR
+RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
+RTCNT_A:	.long	RTCNT
+RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCOR_A:	.long	RTCOR
+RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+SDMR3_A:	.long	SDMR3_ADDRESS
+MCR_A:		.long	MCR
+MCR_D1:		.long	MCR_D1_VALUE
+MCR_D2:		.long	MCR_D2_VALUE
+RFCR_A:		.long	RFCR
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */

board/mpc8568mds/ft_board.c → board/ms7750se/ms7750se.c

@@ -1,5 +1,6 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor.
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -11,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,25 +22,30 @@
  */
 
 #include <common.h>
+#include <asm/processor.h>
 
-#include <ft_build.h>
+int checkboard(void)
+{
+	puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
 
-extern void ft_cpu_setup(void *blob, bd_t *bd);
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int board_late_init(void)
 {
-	u32 *p;
-	int len;
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
+	return 0;
 }
-#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */

board/ms7750se/u-boot.lds

@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}

board/pm854/pm854.c

@@ -45,8 +45,7 @@ long int fixed_sdram(void);
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -79,13 +78,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    int i,x;
 
 	    x = 10;
@@ -133,9 +131,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -229,8 +226,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;

board/pm856/pm856.c

@@ -232,13 +232,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    int i,x;
 
 	    x = 10;
@@ -287,9 +286,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -382,8 +380,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;

board/sbc8560/sbc8560.c

@@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -264,16 +263,15 @@ long int initdram (int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif
 #endif /* 0 */
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur= &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_DDR_DLL)
 	uint temp_ddrdll = 0;
@@ -336,8 +334,7 @@ long int initdram (int board_type)
 		 * enable errors */
 		uint *p = 0;
 		uint i = 0;
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 		dma_init();
 		for (*p = 0; p < (uint *)(8 * 1024); p++) {
 			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -424,8 +421,7 @@ long int fixed_sdram (void)
 #define CFG_DDR_CONTROL 0xc2000000
 
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds		= 0x00000007;
 	ddr->cs1_bnds		= 0x0010001f;

board/stxgp3/stxgp3.c

@@ -203,8 +203,7 @@ int
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -283,11 +282,10 @@ initdram (int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		uint temp_ddrdll = 0;
 
 		/* Work around to stabilize DDR DLL */

board/stxssa/stxssa.c

@@ -252,8 +252,7 @@ int
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile ccsr_pcix_t *pci = &immr->im_pcix;
+	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
 	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -302,8 +301,7 @@ initdram (int board_type)
 
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		uint temp_ddrdll = 0;
 
 		/* Work around to stabilize DDR DLL */

board/tqm85xx/sdram.c

@@ -57,8 +57,7 @@ int cas_latency(void);
 long int sdram_setup(int casl)
 {
 	int i;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
 	unsigned long cfg_ddr_timing1;
 	unsigned long cfg_ddr_mode;
 
@@ -150,8 +149,7 @@ long int initdram (int board_type)
 	 * This DLL-Override only used on TQM8540 and TQM8560
 	 */
 	{
-		volatile immap_t *immap = (immap_t *) CFG_IMMR;
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		int i,x;
 
 		x = 10;

board/tqm85xx/tqm85xx.c

@@ -262,8 +262,7 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	/*
 	 * Adjust flash start and offset to detected values
@@ -324,9 +323,8 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;

board/tqm8xx/flash.c

@@ -33,6 +33,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
+
 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
     && !defined(CONFIG_TQM885D)
 # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
@@ -828,3 +830,5 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 
 /*-----------------------------------------------------------------------
  */
+
+#endif /* !defined(CFG_FLASH_CFI_DRIVER) */

board/tqm8xx/tqm8xx.c

@@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFFFFF
 
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
 const uint sdram_table[] =
 {
 	/*
@@ -63,14 +64,14 @@ const uint sdram_table[] =
 	/*
 	 * Single Write. (Offset 18 in UPMA RAM)
 	 */
-	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+	0x1FF5FC47, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	/*
 	 * Burst Write. (Offset 20 in UPMA RAM)
 	 */
 	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
-					    _NOT_USED_,
+	0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	/*
@@ -83,7 +84,7 @@ const uint sdram_table[] =
 	/*
 	 * Exception. (Offset 3c in UPMA RAM)
 	 */
-	0x7FFFFC07, /* last */
+	0xFFFFFC07, /* last */
 		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 };
 
@@ -183,7 +184,7 @@ long int initdram (int board_type)
 #ifndef	CONFIG_CAN_DRIVER
 	if ((board_type != 'L') &&
 	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
 		memctl->memc_or3 = CFG_OR3_PRELIM;
 		memctl->memc_br3 = CFG_BR3_PRELIM;
 	}
@@ -259,7 +260,7 @@ long int initdram (int board_type)
 #ifndef	CONFIG_CAN_DRIVER
 	if ((board_type != 'L') &&
 	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
 		/*
 		 * Check Bank 1 Memory Size
 		 * use current column settings

common/Makefile

@@ -55,7 +55,7 @@ COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
 COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
 COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
 COBJS-y += cmd_fdc.o
-COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o
+COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
 COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
 COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
 ifdef CONFIG_FPGA
@@ -105,7 +105,6 @@ COBJS-y += env_onenand.o
 COBJS-y += env_nvram.o
 COBJS-y += env_nowhere.o
 COBJS-y += exports.o
-COBJS-y += fdt_support.o
 COBJS-y += flash.o
 COBJS-y += fpga.o
 COBJS-y += ft_build.o

common/cmd_bootm.c

@@ -260,6 +260,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (hdr->ih_arch != IH_CPU_NIOS2)
 #elif defined(__PPC__)
 	if (hdr->ih_arch != IH_CPU_PPC)
+#elif defined(__sh__)
+	if (hdr->ih_arch != IH_CPU_SH)
 #else
 # error Unknown CPU type
 #endif

common/cmd_fdt.c

@@ -588,7 +588,7 @@ static int fdt_print(const char *pathp, char *prop, int depth)
 			printf("%s %s\n", pathp, prop);
 			return 0;
 		} else if (len > 0) {
-			printf("%s=", prop);
+			printf("%s = ", prop);
 			print_data (nodep, len);
 			printf("\n");
 			return 0;
@@ -649,7 +649,7 @@ static int fdt_print(const char *pathp, char *prop, int depth)
 						pathp);
 			} else {
 				if (level <= depth) {
-					printf("%s%s=",
+					printf("%s%s = ",
 						&tabs[MAX_LEVEL - level],
 						pathp);
 					print_data (nodep, len);

common/cmd_ide.c

@@ -886,7 +886,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
 #endif	/* __LITTLE_ENDIAN || CONFIG_AU1X00 */
 
 
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
 static void
 output_data(int dev, ulong *sect_buf, int words)
 {
@@ -938,7 +938,7 @@ output_data(int dev, ulong *sect_buf, int words)
 }
 #endif	/* __PPC__ */
 
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
 static void
 input_data(int dev, ulong *sect_buf, int words)
 {

common/fdt_support.c

@@ -24,13 +24,11 @@
 #include <common.h>
 #include <linux/ctype.h>
 #include <linux/types.h>
-
-#ifdef CONFIG_OF_LIBFDT
-
 #include <asm/global_data.h>
 #include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <exports.h>
 
 /*
  * Global data (for the gd->bd)
@@ -70,6 +68,43 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
 	return fdt_setprop(fdt, nodeoff, prop, val, len);
 }
 
+#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
+static int fdt_fixup_stdout(void *fdt, int choosenoff)
+{
+	int err = 0;
+#ifdef CONFIG_CONS_INDEX
+	int node;
+	char sername[9] = { 0 };
+	const char *path;
+
+	sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
+
+	err = node = fdt_path_offset(fdt, "/aliases");
+	if (node >= 0) {
+		int len;
+		path = fdt_getprop(fdt, node, sername, &len);
+		if (path) {
+			char *p = malloc(len);
+			err = -FDT_ERR_NOSPACE;
+			if (p) {
+				memcpy(p, path, len);
+				err = fdt_setprop(fdt, choosenoff,
+					"linux,stdout-path", p, len);
+				free(p);
+			}
+		} else {
+			err = len;
+		}
+	}
+#endif
+	if (err < 0)
+		printf("WARNING: could not set linux,stdout-path %s.\n",
+				fdt_strerror(err));
+
+	return err;
+}
+#endif
+
 int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 {
 	int   nodeoffset;
@@ -160,6 +195,11 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 			printf("WARNING: could not set linux,initrd-end %s.\n",
 				fdt_strerror(err));
 	}
+
+#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
+	err = fdt_fixup_stdout(fdt, nodeoffset);
+#endif
+
 #ifdef OF_STDOUT_PATH
 	err = fdt_setprop(fdt, nodeoffset,
 		"linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
@@ -441,6 +481,87 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
 	do_fixup_by_compat(fdt, compat, prop, &val, 4, create);
 }
 
+int fdt_fixup_memory(void *blob, u64 start, u64 size)
+{
+	int err, nodeoffset, len = 0;
+	u8 tmp[16];
+	const u32 *addrcell, *sizecell;
+
+	err = fdt_check_header(blob);
+	if (err < 0) {
+		printf("%s: %s\n", __FUNCTION__, fdt_strerror(err));
+		return err;
+	}
+
+	/* update, or add and update /memory node */
+	nodeoffset = fdt_path_offset(blob, "/memory");
+	if (nodeoffset < 0) {
+		nodeoffset = fdt_add_subnode(blob, 0, "memory");
+		if (nodeoffset < 0)
+			printf("WARNING: could not create /memory: %s.\n",
+					fdt_strerror(nodeoffset));
+		return nodeoffset;
+	}
+	err = fdt_setprop(blob, nodeoffset, "device_type", "memory",
+			sizeof("memory"));
+	if (err < 0) {
+		printf("WARNING: could not set %s %s.\n", "device_type",
+				fdt_strerror(err));
+		return err;
+	}
+
+	addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+	/* use shifts and mask to ensure endianness */
+	if ((addrcell) && (*addrcell == 2)) {
+		tmp[0] = (start >> 56) & 0xff;
+		tmp[1] = (start >> 48) & 0xff;
+		tmp[2] = (start >> 40) & 0xff;
+		tmp[3] = (start >> 32) & 0xff;
+		tmp[4] = (start >> 24) & 0xff;
+		tmp[5] = (start >> 16) & 0xff;
+		tmp[6] = (start >>  8) & 0xff;
+		tmp[7] = (start      ) & 0xff;
+		len = 8;
+	} else {
+		tmp[0] = (start >> 24) & 0xff;
+		tmp[1] = (start >> 16) & 0xff;
+		tmp[2] = (start >>  8) & 0xff;
+		tmp[3] = (start      ) & 0xff;
+		len = 4;
+	}
+
+	sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
+	/* use shifts and mask to ensure endianness */
+	if ((sizecell) && (*sizecell == 2)) {
+		tmp[0+len] = (size >> 56) & 0xff;
+		tmp[1+len] = (size >> 48) & 0xff;
+		tmp[2+len] = (size >> 40) & 0xff;
+		tmp[3+len] = (size >> 32) & 0xff;
+		tmp[4+len] = (size >> 24) & 0xff;
+		tmp[5+len] = (size >> 16) & 0xff;
+		tmp[6+len] = (size >>  8) & 0xff;
+		tmp[7+len] = (size      ) & 0xff;
+		len += 8;
+	} else {
+		tmp[0+len] = (size >> 24) & 0xff;
+		tmp[1+len] = (size >> 16) & 0xff;
+		tmp[2+len] = (size >>  8) & 0xff;
+		tmp[3+len] = (size      ) & 0xff;
+		len += 4;
+	}
+
+	err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
+	if (err < 0) {
+		printf("WARNING: could not set %s %s.\n",
+				"reg", fdt_strerror(err));
+		return err;
+	}
+	return 0;
+}
+
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+
 void fdt_fixup_ethernet(void *fdt, bd_t *bd)
 {
 	int node;
@@ -486,5 +607,4 @@ void fdt_fixup_ethernet(void *fdt, bd_t *bd)
 #endif
 	}
 }
-
-#endif /* CONFIG_OF_LIBFDT */
+#endif

cpu/at32ap/at32ap7000/gpio.c → cpu/at32ap/at32ap700x/gpio.c

@@ -21,6 +21,7 @@
  */
 #include <common.h>
 
+#include <asm/arch/chip-features.h>
 #include <asm/arch/gpio.h>
 
 /*
@@ -52,6 +53,7 @@ void gpio_enable_ebi(void)
 #endif
 }
 
+#ifdef AT32AP700x_CHIP_HAS_USART
 void gpio_enable_usart0(void)
 {
 	gpio_select_periph_B(GPIO_PIN_PA8, 0);
@@ -72,10 +74,12 @@ void gpio_enable_usart2(void)
 
 void gpio_enable_usart3(void)
 {
+	gpio_select_periph_B(GPIO_PIN_PB17, 0);
 	gpio_select_periph_B(GPIO_PIN_PB18, 0);
-	gpio_select_periph_B(GPIO_PIN_PB19, 0);
 }
+#endif
 
+#ifdef AT32AP700x_CHIP_HAS_MACB
 void gpio_enable_macb0(void)
 {
 	gpio_select_periph_A(GPIO_PIN_PC3,  0);	/* TXD0	*/
@@ -125,7 +129,9 @@ void gpio_enable_macb1(void)
 	gpio_select_periph_B(GPIO_PIN_PD15, 0);	/* SPD	*/
 #endif
 }
+#endif
 
+#ifdef AT32AP700x_CHIP_HAS_MMCI
 void gpio_enable_mmci(void)
 {
 	gpio_select_periph_A(GPIO_PIN_PA10, 0);	/* CLK	 */
@@ -135,3 +141,4 @@ void gpio_enable_mmci(void)
 	gpio_select_periph_A(GPIO_PIN_PA14, 0);	/* DATA2 */
 	gpio_select_periph_A(GPIO_PIN_PA15, 0);	/* DATA3 */
 }
+#endif

cpu/at32ap/atmel_mci.c

@@ -198,11 +198,11 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
 
 	/* Put the device into Transfer state */
 	ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
-	if (ret) goto fail;
+	if (ret) goto out;
 
 	/* Set block length */
 	ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
-	if (ret) goto fail;
+	if (ret) goto out;
 
 	pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
 
@@ -211,7 +211,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
 			      start * mmc_blkdev.blksz, resp,
 			      (R1 | NCR | TRCMD_START | TRDIR_READ
 			       | TRTYP_BLOCK));
-		if (ret) goto fail;
+		if (ret) goto out;
 
 		ret = -EIO;
 		wordcount = 0;
@@ -219,7 +219,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
 			do {
 				status = mmci_readl(SR);
 				if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
-					goto fail;
+					goto read_error;
 			} while (!(status & MMCI_BIT(RXRDY)));
 
 			if (status & MMCI_BIT(RXRDY)) {
@@ -244,9 +244,10 @@ out:
 	mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
 	return i;
 
-fail:
+read_error:
 	mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
-	printf("mmc: bread failed, card status = %08x\n", card_status);
+	printf("mmc: bread failed, status = %08x, card status = %08x\n",
+	       status, card_status);
 	goto out;
 }
 

cpu/mpc83xx/cpu.c

@@ -35,6 +35,7 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
+#include <fdt_support.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -526,7 +527,6 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	int nodeoffset;
 	int err;
 	int j;
-	int tmp[2];
 
 	for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
 		nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
@@ -543,21 +543,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		}
 	}
 
-	/* update, or add and update /memory node */
-	nodeoffset = fdt_path_offset(blob, "/memory");
-	if (nodeoffset < 0) {
-		nodeoffset = fdt_add_subnode(blob, 0, "memory");
-		if (nodeoffset < 0)
-			debug("failed to add /memory node: %s\n",
-			      fdt_strerror(nodeoffset));
-	}
-	if (nodeoffset >= 0) {
-		fdt_setprop(blob, nodeoffset, "device_type",
-			    "memory", sizeof("memory"));
-		tmp[0] = cpu_to_be32(bd->bi_memstart);
-		tmp[1] = cpu_to_be32(bd->bi_memsize);
-		fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
-	}
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
 void

cpu/mpc85xx/Makefile

@@ -29,8 +29,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o resetvec.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
+	  pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
+	  $(COBJS-y)
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

cpu/mpc85xx/commproc.c

@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 void
 m8560_cpm_reset(void)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	volatile ulong count;
 
 	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
@@ -50,11 +50,11 @@ m8560_cpm_reset(void)
 	/*
 	 * Reset CPM
 	 */
-	immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
+	cpm->im_cpm_cp.cpcr = CPM_CR_RST;
 	count = 0;
 	do {			/* Spin until command processed		*/
 		__asm__ __volatile__ ("eieio");
-	} while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
+	} while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
 }
 
 /* Allocate some memory from the dual ported ram.
@@ -64,7 +64,7 @@ m8560_cpm_reset(void)
 uint
 m8560_cpm_dpalloc(uint size, uint align)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	uint	retloc;
 	uint	align_mask, off;
 	uint	savebase;
@@ -86,7 +86,7 @@ m8560_cpm_dpalloc(uint size, uint align)
 	retloc = gd->dp_alloc_base;
 	gd->dp_alloc_base += size;
 
-	memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
+	memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
 
 	return(retloc);
 }
@@ -120,16 +120,16 @@ m8560_cpm_hostalloc(uint size, uint align)
 void
 m8560_cpm_setbrg(uint brg, uint rate)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	volatile uint	*bp;
 
 	/* This is good enough to get SMCs running.....
 	*/
 	if (brg < 4) {
-		bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
 	}
 	else {
-		bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
 		brg -= 4;
 	}
 	bp += brg;
@@ -142,16 +142,16 @@ m8560_cpm_setbrg(uint brg, uint rate)
 void
 m8560_cpm_fastbrg(uint brg, uint rate, int div16)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	volatile uint	*bp;
 
 	/* This is good enough to get SMCs running.....
 	*/
 	if (brg < 4) {
-		bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
 	}
 	else {
-		bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
 		brg -= 4;
 	}
 	bp += brg;
@@ -167,14 +167,14 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16)
 void
 m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	volatile uint	*bp;
 
 	if (brg < 4) {
-		bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
 	}
 	else {
-		bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
 		brg -= 4;
 	}
 	bp += brg;

cpu/mpc85xx/cpu.c

@@ -30,11 +30,6 @@
 #include <command.h>
 #include <asm/cache.h>
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
-
 int checkcpu (void)
 {
 	sys_info_t sysinfo;
@@ -44,6 +39,8 @@ int checkcpu (void)
 	uint fam;
 	uint ver;
 	uint major, minor;
+	u32 ddr_ratio;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 	svr = get_svr();
 	ver = SVR_VER(svr);
@@ -107,14 +104,25 @@ int checkcpu (void)
 	puts("Clock Configuration:\n");
 	printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
 	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
-	printf("       DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+	ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+	switch (ddr_ratio) {
+	case 0x0:
+		printf("       DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
+		break;
+	case 0x7:
+		printf("       DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
+		break;
+	default:
+		printf("       DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
+		break;
+	}
 
 #if defined(CFG_LBC_LCRR)
 	lcrr = CFG_LBC_LCRR;
 #else
 	{
-	    volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	    volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	    volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	    lcrr = lbc->lcrr;
 	}
@@ -214,8 +222,7 @@ reset_85xx_watchdog(void)
 
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void) {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 
 	dma->satr0 = 0x02c40000;
 	dma->datr0 = 0x02c40000;
@@ -225,8 +232,7 @@ void dma_init(void) {
 }
 
 uint dma_check(void) {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 	volatile uint status = dma->sr0;
 
 	/* While the channel is busy, spin */
@@ -245,8 +251,7 @@ uint dma_check(void) {
 }
 
 int dma_xfer(void *dest, uint count, void *src) {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 
 	dma->dar0 = (uint) dest;
 	dma->sar0 = (uint) src;
@@ -258,94 +263,3 @@ int dma_xfer(void *dest, uint count, void *src) {
 	return dma_check();
 }
 #endif
-
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_cpu_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	ulong clock;
-	int len;
-
-	clock = bd->bi_busfreq;
-	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-	p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
-	if (p != NULL)
-		*p = cpu_to_be32(clock);
-
-#if defined(CONFIG_HAS_ETH0)
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enetaddr, 6);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enetaddr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH1)
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet1addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet1addr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH2)
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet2addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet2addr, 6);
-
-#ifdef CONFIG_UEC_ETH
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet2addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet2addr, 6);
-
-#endif
-#endif
-
-#if defined(CONFIG_HAS_ETH3)
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet3addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet3addr, 6);
-
-#ifdef CONFIG_UEC_ETH
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet3addr, 6);
-
-	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
-	if (p)
-		memcpy(p, bd->bi_enet3addr, 6);
-
-#endif
-#endif
-
-}
-#endif

cpu/mpc85xx/cpu_init.c

@@ -59,7 +59,7 @@ static void config_qe_ioports(void)
 #endif
 
 #ifdef CONFIG_CPM2
-static void config_8560_ioports (volatile immap_t * immr)
+void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 {
 	int portnum;
 
@@ -99,7 +99,7 @@ static void config_8560_ioports (volatile immap_t * immr)
 		}
 
 		if (pmsk != 0) {
-			volatile ioport_t *iop = ioport_addr (immr, portnum);
+			volatile ioport_t *iop = ioport_addr (cpm, portnum);
 			uint tpmsk = ~pmsk;
 
 			/*
@@ -131,8 +131,7 @@ static void config_8560_ioports (volatile immap_t * immr)
 
 void cpu_init_f (void)
 {
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 	extern void m8560_cpm_reset (void);
 
 	/* Pointer is writable since we allocated a register for it */
@@ -143,7 +142,7 @@ void cpu_init_f (void)
 
 
 #ifdef CONFIG_CPM2
-	config_8560_ioports(immap);
+	config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 #endif
 
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
@@ -222,18 +221,15 @@ void cpu_init_f (void)
 
 int cpu_init_r(void)
 {
-#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-#endif
 #ifdef CONFIG_CLEAR_LAW0
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	/* clear alternate boot location LAW (used for sdram, or ddr bank) */
 	ecm->lawar0 = 0;
 #endif
 
 #if defined(CONFIG_L2_CACHE)
-	volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+	volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint svr, ver;
 	uint l2srbar;

cpu/mpc85xx/ether_fcc.c

@@ -230,8 +230,8 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
 {
     struct ether_fcc_info_s * info = dev->priv;
     int i;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
+    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+    volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
     fcc_enet_t *pram_ptr;
     unsigned long mem_addr;
 
@@ -242,35 +242,35 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     /* 28.9 - (1-2): ioports have been set up already */
 
     /* 28.9 - (3): connect FCC's tx and rx clocks */
-    immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
-    immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
+    cpm->im_cpm_mux.cmxuar = 0; /* ATM */
+    cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
 							info->cmxfcr_value;
 
     /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
     if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+	cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
     } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+	cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
     } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+	cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
     }
 
     /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
     if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+	cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
     } else if (info->ether_index == 1){
-	immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+	cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
     } else if (info->ether_index == 2){
-	immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+	cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
     }
 
     /* 28.9 - (6): FDSR: Ethernet Syn */
     if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
+	cpm->im_cpm_fcc1.fdsr = 0xD555;
     } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
+	cpm->im_cpm_fcc2.fdsr = 0xD555;
     } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
+	cpm->im_cpm_fcc3.fdsr = 0xD555;
     }
 
     /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
@@ -296,7 +296,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
     /* 28.9 - (7): initialize parameter ram */
-    pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
+    pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
 
     /* clear whole structure to make sure all reserved fields are zero */
     memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
@@ -385,14 +385,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     /* 28.9 - (8)(9): clear out events in FCCE */
     /* 28.9 - (9): FCCM: mask all events */
     if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
-	immr->im_cpm.im_cpm_fcc1.fccm = 0;
+	cpm->im_cpm_fcc1.fcce = ~0x0;
+	cpm->im_cpm_fcc1.fccm = 0;
     } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
-	immr->im_cpm.im_cpm_fcc2.fccm = 0;
+	cpm->im_cpm_fcc2.fcce = ~0x0;
+	cpm->im_cpm_fcc2.fccm = 0;
     } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
-	immr->im_cpm.im_cpm_fcc3.fccm = 0;
+	cpm->im_cpm_fcc3.fcce = ~0x0;
+	cpm->im_cpm_fcc3.fccm = 0;
     }
 
     /* 28.9 - (10-12): we don't use ethernet interrupts */
@@ -413,11 +413,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
 
     /* 28.9 - (14): enable tx/rx in gfmr */
     if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+	cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
     } else if (info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+	cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
     } else if (info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+	cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
     }
 
     return 1;
@@ -426,15 +426,15 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
 static void fec_halt(struct eth_device* dev)
 {
     struct ether_fcc_info_s * info = dev->priv;
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 
     /* write GFMR: disable tx/rx */
     if(info->ether_index == 0) {
-	immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+	cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
     } else if(info->ether_index == 1) {
-	immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+	cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
     } else if(info->ether_index == 2) {
-	immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+	cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
     }
 }
 

cpu/mpc85xx/fdt.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+	fdt_fixup_ethernet(blob, bd);
+#endif
+
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"timebase-frequency", bd->bi_busfreq / 8, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"clock-frequency", bd->bi_intfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+#ifdef CONFIG_QE
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CFG_NS16550
+	do_fixup_by_compat_u32(blob, "ns16550",
+		"clock-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CONFIG_CPM2
+	do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
+		"current-speed", bd->bi_baudrate, 1);
+
+	do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
+		"clock-frequency", bd->bi_brgfreq, 1);
+#endif
+
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}

cpu/mpc85xx/interrupts.c

@@ -80,19 +80,17 @@ int disable_interrupts (void)
 
 int interrupt_init (void)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
 
-	immr->im_pic.gcr = MPC85xx_PICGCR_RST;
-	while (immr->im_pic.gcr & MPC85xx_PICGCR_RST);
-	immr->im_pic.gcr = MPC85xx_PICGCR_M;
+	pic->gcr = MPC85xx_PICGCR_RST;
+	while (pic->gcr & MPC85xx_PICGCR_RST);
+	pic->gcr = MPC85xx_PICGCR_M;
 	decrementer_count = get_tbclk() / CFG_HZ;
 	mtspr(SPRN_TCR, TCR_PIE);
 	set_dec (decrementer_count);
 	set_msr (get_msr () | MSR_EE);
 
 #ifdef CONFIG_INTERRUPTS
-	volatile ccsr_pic_t *pic = &immr->im_pic;
-
 	pic->iivpr1 = 0x810002;	/* 50220 enable ecm interrupts */
 	debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
 

cpu/mpc85xx/pci.c

@@ -29,10 +29,6 @@
 #include <asm/cpm_85xx.h>
 #include <pci.h>
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
 #if defined(CONFIG_PCI)
 
 static struct pci_controller *pci_hose;
@@ -43,12 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 	u16 reg16;
 	u32 dev;
 
-	volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
-	volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+	volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR);
 #ifdef CONFIG_MPC85XX_PCI2
-	volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
+	volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR);
 #endif
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	struct pci_controller * hose;
 
 	pci_hose = board_hose;
@@ -216,27 +211,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 	hose->last_busno = pci_hose_scan(hose);
 #endif
 }
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = pci_hose[0].first_busno;
-		p[1] = pci_hose[0].last_busno;
-	}
-
-#ifdef CONFIG_MPC85XX_PCI2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = pci_hose[1].first_busno;
-		p[1] = pci_hose[1].last_busno;
-	}
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
 #endif /* CONFIG_PCI */

cpu/mpc85xx/qe_io.c

@@ -34,9 +34,9 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	u32			pin_2bit_assign;
 	u32			pin_1bit_mask;
 	u32			tmp_val;
-	volatile immap_t	*im = (volatile immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t 	*gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	volatile par_io_t	*par_io = (volatile par_io_t *)
-						&(im->im_gur.qe_par_io);
+						&(gur->qe_par_io);
 
 	/* Caculate pin location and 2bit mask and dir */
 	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));

cpu/mpc85xx/serial_scc.c

@@ -88,17 +88,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int serial_init (void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	volatile ccsr_cpm_scc_t *sp;
 	volatile scc_uart_t *up;
 	volatile cbd_t *tbdf, *rbdf;
-	volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
+	volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
 	uint	dpaddr;
 
 	/* initialize pointers to SCC */
 
-	sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+	sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
+	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
 
 	/* Disable transmitter/receiver.
 	*/
@@ -107,8 +107,8 @@ int serial_init (void)
 	/* put the SCC channel into NMSI (non multiplexd serial interface)
 	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
 	 */
-	im->im_cpm.im_cpm_mux.cmxscr = \
-		(im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
+	cpm->im_cpm_mux.cmxscr = \
+		(cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
 
 	/* Set up the baud rate generator.
 	*/
@@ -123,7 +123,7 @@ int serial_init (void)
 	/* Set the physical address of the host memory buffers in
 	 * the buffer descriptors.
 	 */
-	rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
+	rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
 	rbdf->cbd_bufaddr = (uint) (rbdf+2);
 	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
 	tbdf = rbdf + 1;
@@ -201,14 +201,13 @@ serial_putc(const char c)
 {
 	volatile scc_uart_t	*up;
 	volatile cbd_t		*tbdf;
-	volatile immap_t	*im;
+	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 
 	if (c == '\n')
 		serial_putc ('\r');
 
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-	tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
+	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+	tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
 
 	/* Wait for last character to go.
 	 */
@@ -235,12 +234,11 @@ serial_getc(void)
 {
 	volatile cbd_t		*rbdf;
 	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
+	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	unsigned char		c;
 
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-	rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
 
 	/* Wait for character to show up.
 	 */
@@ -260,11 +258,10 @@ serial_tstc()
 {
 	volatile cbd_t		*rbdf;
 	volatile scc_uart_t	*up;
-	volatile immap_t	*im;
+	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 
-	im = (immap_t *)CFG_IMMR;
-	up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
-	rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
 
 	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
 }

cpu/mpc85xx/spd_sdram.c

@@ -53,8 +53,8 @@ picos_to_clk(int picos)
 {
 	int clks;
 
-	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
-	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+	clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
+	if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
 		clks++;
 	}
 
@@ -171,8 +171,7 @@ unsigned int determine_refresh_rate(unsigned int spd_refresh)
 long int
 spd_sdram(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
 	spd_eeprom_t spd;
 	unsigned int n_ranks;
 	unsigned int rank_density;
@@ -309,7 +308,7 @@ spd_sdram(void)
 	if ((SVR_VER(get_svr()) == SVR_8548_E) &&
 			(SVR_MJREV(get_svr()) == 1) &&
 			(spd.mem_type == SPD_MEMTYPE_DDR2)) {
-		volatile ccsr_gur_t *gur = &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		gur->ddrioovcr = (0x80000000	/* Enable */
 				  | 0x10000000);/* VSEL to 1.8V */
 	}
@@ -422,7 +421,7 @@ spd_sdram(void)
 	 * Adjust the CAS Latency to allow for bus speeds that
 	 * are slower than the DDR module.
 	 */
-	busfreq = get_bus_freq(0) / 1000000;	/* MHz */
+	busfreq = get_ddr_freq(0) / 1000000;	/* MHz */
 
 	effective_data_rate = max_data_rate;
 	if (busfreq < 90) {
@@ -1023,8 +1022,7 @@ spd_sdram(void)
 static unsigned int
 setup_laws_and_tlbs(unsigned int memsize)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 	unsigned int tlb_size;
 	unsigned int law_size;
 	unsigned int ram_tlb_index;
@@ -1130,8 +1128,7 @@ ddr_enable_ecc(unsigned int dram_size)
 {
 	uint *p = 0;
 	uint i = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	dma_init();
 

cpu/mpc85xx/speed.c

@@ -35,8 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info (sys_info_t * sysInfo)
 {
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	uint plat_ratio,e500_ratio,half_freqSystemBus;
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -49,6 +48,15 @@ void get_sys_info (sys_info_t * sysInfo)
 	 * overflow for processor speeds above 2GHz */
 	half_freqSystemBus = sysInfo->freqSystemBus/2;
 	sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+	sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+
+#ifdef CONFIG_DDR_CLK_FREQ
+	{
+		u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+		if (ddr_ratio != 0x7)
+			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+	}
+#endif
 }
 
 
@@ -56,12 +64,12 @@ int get_clocks (void)
 {
 	sys_info_t sys_info;
 #if defined(CONFIG_CPM2)
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
 	uint sccr, dfbrg;
 
 	/* set VCO = 4 * BRG */
-	immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
-	sccr = immap->im_cpm.im_cpm_intctl.sccr;
+	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
+	sccr = cpm->im_cpm_intctl.sccr;
 	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 #endif
 	get_sys_info (&sys_info);
@@ -94,3 +102,19 @@ ulong get_bus_freq (ulong dummy)
 
 	return val;
 }
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq (ulong dummy)
+{
+	ulong val;
+
+	sys_info_t sys_info;
+
+	get_sys_info (&sys_info);
+	val = sys_info.freqDDRBus;
+
+	return val;
+}

cpu/mpc85xx/traps.c

@@ -288,8 +288,8 @@ UnknownException(struct pt_regs *regs)
 void
 ExtIntException(struct pt_regs *regs)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_pic_t *pic = &immap->im_pic;
+	volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+
 	uint vect;
 
 #if defined(CONFIG_CMD_KGDB)

cpu/mpc8xx/speed.c

@@ -259,11 +259,8 @@ int get_clocks_866 (void)
 	 */
 	sccr_reg = immr->im_clkrst.car_sccr;
 	sccr_reg &= ~SCCR_EBDF11;
-#if defined(CONFIG_TQM885D)
-	if (gd->cpu_clk <= 80000000) {
-#else
+
 	if (gd->cpu_clk <= 66000000) {
-#endif
 		sccr_reg |= SCCR_EBDF00;	/* bus division factor = 1 */
 		gd->bus_clk = gd->cpu_clk;
 	} else {

cpu/sh4/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).a
+
+START	= start.o
+OBJS	= cpu.o interrupts.o watchdog.o time.o cache.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/sh4/cache.c

@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2()			\
+  do {					\
+    unsigned long __dummy;		\
+    __asm__ __volatile__(		\
+		"mov.l	1f, %0\n\t"	\
+		"or	%1, %0\n\t"	\
+		"jmp	@%0\n\t"	\
+		" nop\n\t"		\
+		".balign 4\n"		\
+		"1:	.long 2f\n"	\
+		"2:"			\
+		: "=&r" (__dummy)	\
+		: "r" (0x20000000));	\
+  } while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1()					\
+  do {							\
+    unsigned long __dummy;				\
+    __asm__ __volatile__(				\
+		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
+  } while (0)
+
+#define CACHE_VALID       1
+#define CACHE_UPDATED     2
+
+static inline void cache_wback_all(void)
+{
+	unsigned long addr, data, i, j;
+
+	jump_to_P2();
+	for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
+		for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+      			addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+				| (i << CACHE_OC_ENTRY_SHIFT);
+      			data = inl(addr);
+			if (data & CACHE_UPDATED) {
+				data &= ~CACHE_UPDATED;
+				outl(data, addr);
+			}
+		}
+	}
+	back_to_P1();
+}
+
+
+#define CACHE_ENABLE      0
+#define CACHE_DISABLE     1
+
+int cache_control(unsigned int cmd)
+{
+	unsigned long ccr;
+
+	jump_to_P2();
+	ccr = inl(CCR);
+
+	if (ccr & CCR_CACHE_ENABLE)
+		cache_wback_all();
+
+	if (cmd == CACHE_DISABLE)
+		outl(CCR_CACHE_STOP, CCR);
+	else
+		outl(CCR_CACHE_INIT, CCR);
+	back_to_P1();
+
+	return 0;
+}

cpu/sh4/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+PLATFORM_CPPFLAGS += -m4-nofpu
+PLATFORM_RELFLAGS += -ffixed-r13

cpu/sh4/cpu.c

@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+int checkcpu(void)
+{
+	puts("CPU: SH4\n");
+	return 0;
+}
+
+int cpu_init (void)
+{
+	return 0;
+}
+
+int cleanup_before_linux (void)
+{
+	disable_interrupts();
+	return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	disable_interrupts();
+	reset_cpu (0);
+	return 0;
+}
+
+void flush_cache (unsigned long addr, unsigned long size)
+{
+
+}
+
+void icache_enable (void)
+{
+	cache_control(0);
+}
+
+void icache_disable (void)
+{
+	cache_control(1);
+}
+
+int icache_status (void)
+{
+	return 0;
+}
+
+void dcache_enable (void)
+{
+}
+
+void dcache_disable (void)
+{
+}
+
+int dcache_status (void)
+{
+	return 0;
+}

cpu/sh4/interrupts.c

@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int interrupt_init (void)
+{
+	return 0;
+}
+
+void enable_interrupts (void)
+{
+
+}
+
+int disable_interrupts (void){
+	return 0;
+}

cpu/sh4/start.S

@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+	.text
+	.align	2
+
+	.global	_start
+_start:
+	mov.l	._lowlevel_init, r0
+100:	bsrf	r0
+	nop
+
+	bsr	1f
+	nop
+1:	sts	pr, r5
+	mov.l	._reloc_dst, r4
+	add	#(_start-1b), r5
+	mov.l	._reloc_dst_end, r6
+
+2:	mov.l	@r5+, r1
+	mov.l	r1, @r4
+	add	#4, r4
+	cmp/hs	r6, r4
+	bf	2b
+
+	mov.l	._bss_start, r4
+	mov.l	._bss_end, r5
+	mov	#0, r1
+
+3:	mov.l	r1, @r4			/* bss clear */
+	add	#4, r4
+	cmp/hs	r5, r4
+	bf	3b
+
+	mov.l	._gd_init, r13		/* global data */
+	mov.l	._stack_init, r15	/* stack */
+
+	mov.l	._sh_generic_init, r0
+	jsr	@r0
+	nop
+
+loop:
+	bra	loop
+
+	.align	2
+
+._lowlevel_init:	.long	(lowlevel_init - (100b + 4))
+._reloc_dst:		.long	reloc_dst
+._reloc_dst_end:	.long	reloc_dst_end
+._bss_start:		.long	bss_start
+._bss_end:		.long	bss_end
+._gd_init:		.long	(_start - CFG_GBL_DATA_SIZE)
+._stack_init:		.long	(_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._sh_generic_init:	.long	sh_generic_init

cpu/sh4/time.c

@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2007
+ * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define TMU_MAX_COUNTER (~0UL)
+
+static void tmu_timer_start (unsigned int timer)
+{
+	if (timer > 2)
+		return;
+
+	*((volatile unsigned char *) TSTR) |= (1 << timer);
+}
+
+static void tmu_timer_stop (unsigned int timer)
+{
+	u8 val = *((volatile u8 *)TSTR);
+	if (timer > 2)
+		return;
+	*((volatile unsigned char *)TSTR) = val &~(1 << timer);
+}
+
+int timer_init (void)
+{
+	/* Divide clock by 4 */
+	*(volatile u16 *)TCR0 = 0;
+
+	tmu_timer_stop(0);
+	tmu_timer_start(0);
+	return 0;
+}
+
+/*
+   In theory we should return a true 64bit value (ie something that doesn't
+   overflow). However, we don't. Therefore if TMU runs at fastest rate of
+   6.75 MHz this value will wrap after u-boot has been running for approx
+   10 minutes.
+*/
+unsigned long long get_ticks (void)
+{
+	return (0 - *((volatile u32 *) TCNT0));
+}
+
+unsigned long get_timer (unsigned long base)
+{
+	return ((0 - *((volatile u32 *) TCNT0)) - base);
+}
+
+void set_timer (unsigned long t)
+{
+	*((volatile unsigned int *) TCNT0) = (0 - t);
+}
+
+void reset_timer (void)
+{
+	tmu_timer_stop(0);
+	set_timer (0);
+	tmu_timer_start(0);
+}
+
+void udelay (unsigned long usec)
+{
+	unsigned int start = get_timer (0);
+	unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
+
+	while (get_timer (0) < end)
+		continue;
+}
+
+unsigned long get_tbclk (void)
+{
+	return CFG_HZ;
+}

cpu/sh4/watchdog.c

@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define WDT_BASE	WTCNT
+
+static unsigned char cnt_read (void){
+	return *((volatile unsigned char *)(WDT_BASE + 0x00));
+}
+
+static unsigned char csr_read (void){
+	return *((volatile unsigned char *)(WDT_BASE + 0x04));
+}
+
+static void cnt_write (unsigned char value){
+	while (csr_read() & (1 << 5)) {
+		/* delay */
+	}
+	*((volatile unsigned short *)(WDT_BASE + 0x00))
+		= ((unsigned short) value) | 0x5A00;
+}
+
+static void csr_write (unsigned char value){
+	*((volatile unsigned short *)(WDT_BASE + 0x04))
+		= ((unsigned short) value) | 0xA500;
+}
+
+
+int watchdog_init (void){ return 0; }
+
+void reset_cpu (unsigned long ignored)
+{
+	while(1);
+}